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78 Cards in this Set
- Front
- Back
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FF |
Is circuit of device containing active elements, capable of assuming one of either two stable states at a given time |
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Latching |
The holding of a circuit at a particular state after it has been driven to that state by an external signal |
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Clock |
A device the generates periodic signals used for timing and synchronization. Also describes the signal produced by the clock. Abbreviated CK or CLK |
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Edge Triggered |
Certain FF that require a change in the clock signal as a condition for switching states |
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Leading Edge |
Low to high change of the clock pulse. Also called up clock |
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Trailing edge |
High to low change in the clock pulse. Also called down clock |
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Characteristics of FF |
They have one to five inputs, depending on the type and application. All have two outputs. |
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When high.... |
Indicates that the FF is in the Set(S) state and storing a binary number of 1. The Q Not output is low or 0. |
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When low... |
The FF is in the RESET(R) state, storing a binary number of 0. The Q Not output is high or 1 |
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Inputs required to change he state are... |
Circuit design, transistors used and manufacturers design. |
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Logic probe is... |
Valuable for troubleshooting digital integrated logic circuits |
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Logic probe is also known as... |
Integrated circuit testing device |
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Ideal Logic probe will... |
Detect a steady logic level, detect a train of logic pulses, detect a high speed transient pulse, detect an open circuit, have over voltage protection, small light and easy to handle, accommodate different logic families |
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Multivibrator |
Circuit that is commonly used for clock or timing pulses. Used to start, stop, or synchronize various circuits in a set or system. |
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Multivibrators produce... |
Balanced and unbalanced square waves |
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Triggered |
Requires a trigger pulse |
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Free-running |
Doesn't require a trigger pulse |
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Astable Multivibrator |
Oscillate at a fixed frequency and have no stable state(free running). Outputs are identical except for polarity inversion. During operation one transistor is cutoff while the other operates. |
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Base Recovery Time |
The time it takes for the RC network to discharge to cutoff |
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Monostable Multivibrator |
Also called one shot. It's a regenerative circuit with one stable condition, Q1off and Q2 on. Countdown is accomplished when ⬆️ in the t of the base circuit and ⬇️ the time b/w the input trigger pulse |
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Bistable Multivibrator |
Also called Eccles-Jordan. Produces the best quality square wave. Two stable states. Often called Flip-Flop. Requires two triggers to complete one cycle, positive or negative. |
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Registers |
A device that is used for the temporary storage of binary data in order to facilitate arithmetic, logic, or data transfer operations. Accomplished the register has to receive data, maintain data until needed, and transfer to other computers as required by computer programs. |
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Register is composed of... |
Bistable elements such as magnetic cores or FF. # of bistable elements is determined by word length. |
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Modulus is determined by... |
Number of stages used. 2n |
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Registers have what mode of access... |
Parallel or serial mode |
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Mode of access is... |
Method of inserting or extracting data into or out of a register. |
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Parallel mode of access is... |
Separate gating circuit for each data bit that's applied to or taken from register. Application of a single read in or read out clock pulse, all data bits transferred simultaneously |
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Serial mode of access is... |
Data bits transferred sequentially over a single gate circuit line. Separate read in or read out pulse required for each date bit. |
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Access time refers to... |
The amount of time between a request to the register for info and the moment it becomes available at the desired location. Access time is dependent on the mode of access. |
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Volatile storage... |
Is when the stored data is lost when the applied power is removed Ex: FF |
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Nonvolatile storage is... |
A storage device that stores data for long periods of time without external power Ex: CD, DVD, hard drives |
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Stored register temporarily... |
Stores binary data until it's called for by other computer circuits. Configured for parallel access, receives data simultaneously. |
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Shift Registers |
Stored data can be shifted left or right with clock or shift pulse. Used for serial to parallel and parallel to serial conversions and x and / of binary #. |
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Serial-to-parallel conversion... |
Data is read into the register serially and read out in parallel |
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Parallel-to-serial |
Data is read into the register in parallel and read out serially |
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All shift registers can be used in... |
the serial-in or serial-out mode, but not all have ll in or ll out capability. |
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Scaling is a method... |
Where data is loaded into a shift register either serially or in parallel and then shifted serially. |
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Scaling is performed to... |
Change the notation or magnitude of s number Change the value of a variable to keep it within the operating range of the computer |
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Most Significant Digit... |
Must not be shifted out of the register |
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Sealed data... |
Is read from the register using the parallel outputs |
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Clocks are... |
Used to ensure proper timing of events Clock pulses are used to enable and disable circuits and permit operations to begin and others to end in a sequence of time. |
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The simplest clock is... |
Free-running multivibrator. Also known as astable multivibrator. |
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Free-running Multivibrator |
Alternates between two states. Output are = in frequency and amp but opp in polarity. Frequency and balance can be changed by changing R2C1 and R3C2 |
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Most modern equipment uses... |
Crystal-controlled oscillators for timing circuitry. |
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Ripple Counter |
Consists of FF in series. Domino effect(Ripple) Also called asynchronous counter. 0000-1111 0-15 Initially all FF are RESET Disadvantage is it takes its time |
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Synchronous Counter |
Controlled by master clock Applied to all FF simultaneously AND gate added to ensure toggle Initially all FF are RESET 000-111 0-7 |
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Decade Counter |
Count in units of 10 0-9 0000-1001 Same as ripple until 1001 10th clock pulse RESETs NAND gate Modulus is 10 |
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Ripple Counter |
Made up of R-S FF. J-K FF too Only one FF can SET at a time then it RESETs. 1,2,3,4 Initially FF1 is SET |
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Down Counter |
Counts from high to low. Also called decrement counter. Low pulse gives 111 initially until 000. Only counter that starts off with all FF SET. 7-0 111-000 |
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Adders are combo of... |
Logic gates that combine binary values to obtain a sum. |
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Adders are classified according to... |
Ability to accept and combine the digits. |
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Quarter adders... |
Add two binary digits but don't produce a carry. |
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Augend is applied to... |
The A input |
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Addend is applied to... |
The B input |
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Adders are composed of... |
Exclusive OR gate and combination of gates |
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Half-Adders are... |
Circuits that combine two binary digits and produce a carry but don't use it. |
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Full-Adders... |
Produces a sum, generates a catty and uses the carry. |
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Serial-Adders |
Derived using adders and FF to process large numbers |
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"A" Register consists of... |
Series configured FF that usually stores the augend and stores the sum after the addition function is complete. |
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"B" Register consists of... |
Series connected FF and stores the addend. |
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"B" Register consists of... |
Series connected FF and stores the addend. |
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Carry FF allows... |
The carry of one bit time to be added in the next bit time.( delays the carry ) |
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"B" Register consists of... |
Series connected FF and stores the addend. |
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Encoder... |
Device that converts analog to digital Commonly call ADC |
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Decoder... |
Is a matrix network where digital inputs produce analog. Also call DAC |
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Resolution... |
Is the smallest change in the analog output voltage that can occur as a result of a change in the digital input. Determined by # of bits |
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Accuracy... |
Is a comparison of the actual output voltage to the theoretical output level. Expressed in % |
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Settling time... |
Time it takes for DAC to settle within +/- 1/2 of LSD final value. |
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Weight... |
Each but of a binary quantity is assigned a weight depending on its position. |
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Carry FF allows... |
The carry of one bit time to be added in the next bit time.( delays the carry ) |
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Parallel-Adding Circuits |
Require one full-adder for addend and augend, except for LSD which uses half-adder bc carry not considered. Advantage is they add numbers right away without delay. Disadvantage is it requires more parts making it expensive. |
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Subtractors are similar to... |
Adders except for the connection of the inputs and the terminology used. |
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Subtractors are classified according to... |
Ability to generate and utilize a burrow. |
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Full-subtractors can be... |
Parallel and serial |
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Quarter-Subtractor.. |
Perform binary subtraction functions but produces false answers when it becomes necessary to burrow from the next place digit in order to perform subtraction. |
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Half-Subtractors... |
Subtracts and gives a correct difference, generates a burrow but doesn't use it. |
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Equation for subtraction and addition is... |
D=ĀB+AB(with line on top😂) |
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Full-Subtractor |
Generates a burrow and utilizes it |
