The Importance Of Digital Signal Processing

Great Essays
ABSTRACT: Multiplications and Accumulations find tremendous applications in the domain of Digital Signal Processing (DSP). On contrast to this, currently there is an immense requirement of hardware dedicated to serve the purpose of speed enhancement. Reversible circuits are being deployed on a large scale to design the Multiply Accumulate units with the advent of quantum computing. In this paper, we present a real time development model of a 4 x 4 Multiply Accumulate unit by exploiting reversible logic for optimizing energy consumption.
KEYWORDS: Multiplications and Accumulations, DSP, Reversible Logic, Reversible Gates, Power Dissipation, Reversible Multiplier.

I. INTRODUCTION One of the most crucial issues of concern in current technology
…show more content…
The energy that gets dissipated is proportionally equivalent to kTln2 joules of energy for one bit of information loss, where k=1.38 x 10-23 J/K is Boltzmann constant and T being the absolute temperature. C H Bennett [2], proposed that the joules of energy will not be dissipated from the system if the operations are performed using reversible logic and the system can reproduce the inputs from the observed outputs. If computations become information lossless then heat dissipation can be reduced. Shivakumar et al., [3] presented basic reversible sequential gates to build large reversible sequential circuits. Compared with previous designs, the garbage values were reduced by a factor of 2 to 6. A novel universal reversible gate is proposed that realizes both NOR and NAND functionalities. Himanshu et al.,[4] proposed novel designs of reversible latches such as D, JK, T and SR. The proposed designs are better in quantum cost and garbage values. Thapiyal et al.[2005] were the first to discuss the complete design of reversible sequential circuits. Shaik et al., [5] presented a 4 x 4 bit reversible multiplier. Partial products were generated using Peres gate. The design consists of 28 gates, 28 constant inputs and 52 garbage outputs. Rangaraju, et al [6] presented a reversible multiplier with a novel gate termed as the RAM gate. This …show more content…
The differentiation between addition and subtraction operations is done by the control signal. This complete circuit requires one reversible half adder/subtractor at the first stage followed by a sequence of 7 full- adder/subtractors.
C. Reversible Accumulator
Accumulator is one of the most widely used devices in present day digital systems. Group of flip-flops basically form a register which is in turn used to store the information in the system. This can be used later during the computation process. Depending on the clock cycle, the shift register will shift the data bit wise.
C.1 Reversible D- Latch
Figure 9 shows the Reversible D- latch which is designed using Fredkin gate which has a quantum cost of 5 and it has one garbage output.
C. 2 Reversible D - Flip-flop
Reversible D – flip-flop designed using two Fredkin gate is as shown in Figure 10. The D flip-flop has a characteristic equation as Q+ = D.Clk+ Q .Clk1. The first Fredkin gate toggles the output and the second Fredkin gate again toggles the output of the first gate, thus we get the input at the output with a delay.
C. 3 Reversible Eight-bit PIPO Shift

Related Documents

  • Decent Essays

    Ecet 340 Week 4

    • 1985 Words
    • 8 Pages

    What is the percent error for the binary answer found in Problem #2? 4. Given an 24 MHz bus speed. Write down the line(s) of instruction which set the ATD1 unit for 2MHz conversion frequency, 10-bit resolution and 8 A-to-D clocks per sample time. 5.…

    • 1985 Words
    • 8 Pages
    Decent Essays
  • Great Essays

    4. PROPOSED WORK This work 16-bit speculative Han-Carlson adder (HCA) is proposed. Speculative prefix adders can be subdivided in five stages: pre-processing, speculative prefix-processing, post-processing, error detection and error correction. The error correction stage is off the critical path, as it has two clock cycles to obtain the exact sum when speculation fails. 4.1 Pre-processing stage The propagate and generate signals are computed as in equations (1) & (2).…

    • 1491 Words
    • 6 Pages
    Great Essays
  • Improved Essays

    On the first three disks we have the binary information 1010, 1100 and 0011, here representing some data, and now calculate the parity information for the fourth disk. We use XOR operation to calculate the Parity bit: For the first column of the disks, to the left we have 1, 1 and 0: 1XOR 1 XOR 0 = Parity bit Broken down: 1 XOR 1 = 0 and then 0 XOR 0 = The parity bit is 0. This means first 1 XOR 1…

    • 572 Words
    • 3 Pages
    Improved Essays
  • Great Essays

    1. The 10 kΩ potentiometer’s centre pin is connected to the analog input pin. When the shaft of the potentiometer is rotate in a circular direction, the amount of resistance changes on either side of the wiper which is attached to the signal pin of the potentiometer. This tends to changes of the relative closeness of the pin to 5volts and ground, and it gives different analog input. When the potentiometer’s shaft is rotated in circular direction up to 360deg, we read 0 as there is supply of 0volts to the pin.…

    • 1504 Words
    • 7 Pages
    Great Essays
  • Improved Essays

    Flip Flop Case Study

    • 933 Words
    • 4 Pages

    The above factors have been researched in the literature survey while choosing the single edge triggered vs. double edge triggered flip flop, the rise time and fall time that must be allocated to the input waveform to get a good output from the D flip flop. 1.4 MOTIVATION FOR PROJECT Electronic gadgets which are made to be used with minimum human invention and with multiple functionalities occupying minimum area (smart gadgets such as smart phones, smart cars with a lot of self correcting abilities, etc.,) are in huge demand today. Having multiple functionality demands a proportional increase in the memory which can be humongous in some cases. The D flip flop is the basic unit of memory storage. Hence optimization of the D flip flop impacts the IC circuit as a whole.…

    • 933 Words
    • 4 Pages
    Improved Essays
  • Improved Essays

    The Motherboard: The motherboard is the connection between all of the components. The motherboard has many form factors, these will determine where the components go and the shape of the computer case. The most common motherboard form factors will either be Micro-ATX, Mini-ATX and ATX. The difference between these is the amount of expansion slots, and features. However this does depend on the more advanced motherboard you get.…

    • 1393 Words
    • 6 Pages
    Improved Essays
  • Superior Essays

    [25]. Speedup (Sp) = 1/fs + fp/p Where: fs= serial fraction of code fp= parallel fraction of code P= number of processors Suppose serial fraction of code (0.5), parallel fraction of code (0.5) and number of processors (2, 4, 8, 16, 32, 64, 128, 256, 512, and 1024). If P=2: Sp= 1 / (0.5+0.25) = 1.33 Table 1: PPSO algorithm P SP PPSO Elapsed Time 2 1.33 0.02 4 1.60 0.017 8 1.79 0.012 16 1.89 0.008 32 1.96 0.005 64 2.00 0.003 128 2.00 0.002 256 2.00…

    • 1263 Words
    • 6 Pages
    Superior Essays
  • Decent Essays

    Referencing: “Central Processing Unit is the electronic circuiting within a Computer that carries out the instructions of a Computer by preforming the basic arithmetic.” https://en.wikipedia.org/wiki/Central_processing_unit RAM: Random Access Memory is a form of data storage device it is designed to allow data items to be Read / Written to in order to correspond with other peripherals such as HDD, SSD, Optical Drive (DVD-RW) (CD-RW) the read and write rate varies on the size of the chip some manufactures build there chips faster than others so it always best to shop around other types of memory include ROM & NOR-FLASH these types have limits and do not allow data to be wrote to them. Optical Disk…

    • 729 Words
    • 3 Pages
    Decent Essays
  • Superior Essays

    Due to this, the study of new strategies of parallelization, designed to a especific architecture or to a combination of architectures, has become the focus of efforts to accelerate the simulation of particle methods. The GPU was initially designed to accelerate graphics processing, nevertheless, from the mid-2000s, it becomes a more generalized computing device that promises accelerate codes that demand high computational power at lower cost. Despite the known challenges to speedup linear system solutions using GPU, in 2011, Hori et al. cite{Hori-2011} developed a GPU-accelerated version of standard MPS code. The authors shown that, for simulations of two-dimensions model of moderate size (until 100K particles), the GPU-accelerated was about 10 times fast than the code for CPU only.…

    • 1623 Words
    • 7 Pages
    Superior Essays
  • Superior Essays

    Since IPv4 is binary-based, it can be converted to a decimal number from 0 to 255. For example, an IPv4 address is 11000000 10101000 00000111 00011011. The number converted into a decimal format is 192.168.7.27. The volume that 32 bits can present is 232 that are equal to 4,294,967,296. (Defense Advanced Research Projects 1981) IPv6 address owns 16 bytes that are equal to 128 bits…

    • 771 Words
    • 4 Pages
    Superior Essays