KEYWORDS: Multiplications and Accumulations, DSP, Reversible Logic, Reversible Gates, Power Dissipation, Reversible Multiplier.
I. INTRODUCTION One of the most crucial issues of concern in current technology …show more content…
The energy that gets dissipated is proportionally equivalent to kTln2 joules of energy for one bit of information loss, where k=1.38 x 10-23 J/K is Boltzmann constant and T being the absolute temperature. C H Bennett , proposed that the joules of energy will not be dissipated from the system if the operations are performed using reversible logic and the system can reproduce the inputs from the observed outputs. If computations become information lossless then heat dissipation can be reduced. Shivakumar et al.,  presented basic reversible sequential gates to build large reversible sequential circuits. Compared with previous designs, the garbage values were reduced by a factor of 2 to 6. A novel universal reversible gate is proposed that realizes both NOR and NAND functionalities. Himanshu et al., proposed novel designs of reversible latches such as D, JK, T and SR. The proposed designs are better in quantum cost and garbage values. Thapiyal et al. were the first to discuss the complete design of reversible sequential circuits. Shaik et al.,  presented a 4 x 4 bit reversible multiplier. Partial products were generated using Peres gate. The design consists of 28 gates, 28 constant inputs and 52 garbage outputs. Rangaraju, et al  presented a reversible multiplier with a novel gate termed as the RAM gate. This …show more content…
The differentiation between addition and subtraction operations is done by the control signal. This complete circuit requires one reversible half adder/subtractor at the first stage followed by a sequence of 7 full- adder/subtractors.
C. Reversible Accumulator
Accumulator is one of the most widely used devices in present day digital systems. Group of flip-flops basically form a register which is in turn used to store the information in the system. This can be used later during the computation process. Depending on the clock cycle, the shift register will shift the data bit wise.
C.1 Reversible D- Latch
Figure 9 shows the Reversible D- latch which is designed using Fredkin gate which has a quantum cost of 5 and it has one garbage output.
C. 2 Reversible D - Flip-flop
Reversible D – flip-flop designed using two Fredkin gate is as shown in Figure 10. The D flip-flop has a characteristic equation as Q+ = D.Clk+ Q .Clk1. The first Fredkin gate toggles the output and the second Fredkin gate again toggles the output of the first gate, thus we get the input at the output with a delay.
C. 3 Reversible Eight-bit PIPO Shift