Circuit Techniques For Implement Ddr I / O Circuit Design That Can Support Multiple Low Power Standards

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Abstract—This paper presents novel circuit techniques to implement DDR I/O circuit design that can support multiple low-power standards in a state-of-art 7nm CMOS finfet process. Hybrid pull-up driver with a power gating switch is proposed to support a wide range of data rates and output swing levels. The usage of both thin and thick gate oxide devices in the final output stage effectively achieves minimal power consumption while enabling 6.4Gbps/pin data rate. The proposed input receiver directly converts the incoming signal’s common mode levels to the optimal level of the 1st stage amplifier by a replica feedback loop. Frequency peaking technique is also employed to suppress the inter-symbol interference (ISI) and increase overall bandwidth of the receiver. Simulation results are provided.
Keywords—LPDDR; output driver; level translation, input receiver, frequency peaking, active inductor
I. INTRODUCTION
The ever-increasing need for higher bandwidth and lower power consumption for memory subsystem in mobile application is making the market more and more complicated. Although LPDDR4 succeeded in making a soft landing in the high-end mobile handset, quenching the thirst for higher bandwidth than LPDDR3 [1], major memory chip vendors have finished their LPDDR4X preparations to realize even lower overall system power consumption. Moreover, post LPDDR4/LPDDR4X is on its way to debut with 6.4Gbps/pin data bandwidth in the near future, promising better user experience.
This…

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