Circuit Techniques For Implement Ddr I / O Circuit Design That Can Support Multiple Low Power Standards
Keywords—LPDDR; output driver; level translation, input receiver, frequency peaking, active inductor
The ever-increasing need for higher bandwidth and lower power consumption for memory subsystem in mobile application is making the market more and more complicated. Although LPDDR4 succeeded in making a soft landing in the high-end mobile handset, quenching the thirst for higher bandwidth than LPDDR3 , major memory chip vendors have finished their LPDDR4X preparations to realize even lower overall system power consumption. Moreover, post LPDDR4/LPDDR4X is on its way to debut with 6.4Gbps/pin data bandwidth in the near future, promising better user experience.