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295 Cards in this Set
- Front
- Back
describe opcode 1xx
|
add - 1=opcode xx=operand
|
|
which opcodes are branch
|
BRA 6xx
BRZ 7xx BRP 8xx |
|
name all the instructions and which position they're in
|
ADD 1
SUB 2 STA/STO 3 LDA 5 BRA 6 BRZ 7 BRP 8 INP 901 OUT 902 "ass load of bras in brazil, brp, in out" |
|
prom
|
programmable ROM
volatile |
|
eprom
|
non volitile; specific UV light to erase
|
|
eeprom
|
non volatile; electric erasable
|
|
PC to MAR
MDR to IR IR to MAR A- MDR -> A PC +1 to PC |
subtract
|
|
pc to mar
mdr to ir inbox to a pc +1 to pc |
IN
|
|
pc to mar
mdr to ir a to outbox pc +1 to pc |
out
|
|
pc to mar
mdr to ir |
halt
|
|
pc to mar
mdr to ir ir to pc |
branch
|
|
pc to mar
mdr to ir if a=0:ir to pc else: pc1 to pc |
branch zero
|
|
pc to mar
mdr to ir if a ≥ 0: ir to pc else: pc1 to pc |
branch pos
|
|
pc to mar
mdr to ir ir to mar A+ mdr to A pc +1 to pc |
add/fetch execute
|
|
2 types of busses
|
single point and multi point
|
|
risc means...
|
reduced instr set processor
|
|
risc computers have a __ bit word, and is ___ bytes
|
32 bit
4 bytes |
|
cisc means
|
complex instruction set computer
|
|
cisc computers have ___ data words
|
variable length
|
|
cisc computers ___ byte instructions
|
16 byte
|
|
stacks are ordered this way
|
LIFO
|
|
PC to mar
MDR to IR pc1 to pc ir [addr] to pc |
Call stack (push)
|
|
pc to mar
mdr to IR stack to pc |
return (pop)
|
|
which type of computer has 8 gen purpose registers
|
cisc
|
|
which type of computer has 32 gen purpose registers
|
risc
|
|
which computer has 64 gen purpose registers
|
VLIW
|
|
type of computer has 3 48 bit/128bit instruction
|
EPIC
|
|
type of computer has few address nodes
|
RISC
|
|
type of computer has 128 bit molequl and 4 32 bit atoms
|
VLIW
|
|
type of computer that has a code morphing layer
|
VLIW
|
|
Carusoe CPU
|
VLIW
|
|
parallel instruction x4
|
VLIW
|
|
type of computer, 5 bits to ID type of instruction
|
EPIC
|
|
itanium based cpu
|
EPIC
|
|
IRQ 8
|
system cmos/realtime clock
|
|
"here i am" address included in interrupt
|
vector data word
|
|
polls each device after interupt sig
|
polled interupt
|
|
unstoppable interupt
|
non-maskable interupt
|
|
cpu releases control of the bus
|
DMA
|
|
what does the cpu need to know when releasing for DMA
|
how big, where:
location of data on device starting location size of block (512 byte blocks) direction (read or write) |
|
order storage in speed/storage size
|
registers
cache (sram) ram (dram) flash mag disk opt disk mag tape |
|
name storage on a HD
|
sectors
tracks blocks (smallest, 512bytes) Cylinders |
|
2 types of velocity on a HD
|
constant angular velocity
(bits on each track are the same) (same speed every track) Constant linear velocity |
|
time a HD takes to transfer tracks
|
seek time
|
|
time it takes a HD to rotate to the beginning of a sector
|
latency
|
|
time it takes a HD to read data
|
transfer time
|
|
describe the anatomy of a HD block
|
gap|header | data |gap
|
|
how many cycles to read a HD in non-interleaving
|
8 cycles
|
|
spaced out blocks on a HD spacing time for error checks is called ___
|
interleaving
|
|
interleaving reduced the amount of rotations on a HD from ___ to ___
|
8 to 3
|
|
Raid 0
|
striping
|
|
raid 1
|
mirroring
|
|
raid 3
|
striping with dedicated parity
|
|
raid 5
|
striping and distributed parity
|
|
LMC has ___ mailboxes
|
100
|
|
when the source and destination are part of the command
|
explicit addressing
|
|
when the source or destination is not specified as an arguement but are part of the opcodes
|
implicit addressing
|
|
instructions reserved for the OS
|
priviliged
|
|
instructions that can be used by any program
|
non-privilaged
|
|
shift and rotate bits
|
to multiply or divide by 2
|
|
type of computer that has comparatively few general purpose registers
|
CISC
|
|
large number of varying addressing techs, specialized instructions, instruction words of varying sizes
|
cisc
|
|
many gen. purpose registers
|
RISC
|
|
only a few basic load and store instructions, most instructions operate only with registers
|
RISC
|
|
3 types of memory enhancements
|
wide path memory access
memory interleaving cache (write thru/write back) |
|
cpu changes a memory location, main memory is changed at the same time
|
write thru cache
|
|
main memory is not changed until cache is no longer needed, then copied back to main memory... faster
|
write back cache
|
|
a pair of registers in the cpu are connected via bus to the I/O module
|
programmed I/O
|
|
how many IRQ's are there
|
32 (0-31)
|
|
amount of time between timer interupts
|
quantum
|
|
2 types of abmormal event signal
|
power interupt
divide by zero |
|
3 conditions for DMA
|
1 memory and the I/O must be connected
2 I/O module must be capable of accessing memory 3 way to control access to bus and memory so one thing is in memory at a time |
|
IBM mainframe uses ____ to manage I/O to CPU/Memory
|
Channels
|
|
pie shaped selection on a HD
|
sector
|
|
like a floppy, 3000 rpm
|
bernoulli
|
|
explain why write back cache is better
|
faster of the 2
one time write back to memory (vulnerable to power loss) |
|
explain why write thru is worse
|
must update L1, L2, main memory
|
|
used to move data across busses
|
programmed I/O
|
|
which bus was developed as a topology by apple
|
firewire
|
|
multiple paths via independent cpu, to main cpu
|
mainframe channeling
|
|
what is the NIC in an ibm mainframe
|
NIU (net interface Unit)
|
|
what are i/o modules
|
buffers, controls disks, registers and controls DMA, interupts cpu, copies from buffer to disks
|
|
storage heiarchy
|
fastest to increasing storage:
registers cache (SRAM) ram (DRAM) flash magnetic disc optical magnetic tape |
|
cash ram
|
SRAM
|
|
ram type
|
dram
|
|
HD block size
|
512
|
|
what is constant angular velocity
|
bits on each track are the same
same speed on every track |
|
name the parts of a processor
|
accumulator, memory, registers
|
|
instruction size decreases memory size t/f
|
false
|
|
this increases efficiency
|
stack
|
|
port 79
|
finger
|
|
port 23
|
telnet
|
|
port 80
|
http
|
|
ftp data port
|
20
|
|
ftp control port
|
21
|
|
port 110
|
pop
|
|
port 25
|
smtp
|
|
2 types of magnetic tape
|
sequential and linear
|
|
type of mag tape where head rotates
|
helical
|
|
media with 650 mb storage (typical)
|
optical
|
|
optical block size
|
2352
|
|
whats a 1 and 0 represented by in an optical drive
|
land and pit
|
|
whats a land represent on an optical drive
|
flat = 1
|
|
whats a pit represent on an optical drive
|
scatter = 0
|
|
what uses exotic crystaline metal alloys
|
magneto optical
|
|
magneto optical has what difficiency
|
slow seek
|
|
ascii has _ and _ bit words
|
7/8
|
|
ascii hex that would indicate a windows machine
|
0A 0D
|
|
ascii hex that would indicate a unix machine
|
0A
|
|
ascii that starts the alphabet
|
41 (capital letters)
|
|
ascii alphabet
|
41 + 26 = caps alphabet
61 starts lower case |
|
ascii numbers
|
30 - 39 = 1-9
|
|
ascii blank space
|
FF
|
|
ascii periods
|
2E
|
|
encoding on mainframes
|
epcidic
|
|
whats epcidic stand for
|
extended binary code decimal interchange code
|
|
whats ascii stand for
|
american standard code for information interchange
|
|
whats BCD
|
binary coded decimal
|
|
write out 253 in BCD
|
0010 0101 0011
|
|
name the 5 ways to increase system performance
|
1 multiple cpu
2 clock speed 3 wide instruction/data path 4 disk access 5 increase memory |
|
whats tight coupled multiprocessing
|
multiple cpus share common resources like memory and I/O.
|
|
what is loosely coupled multiprocessing
|
each cpu has memory and I/O devices (clusters)
|
|
what is master slave multiprocessing
|
one cpu is reserved for the OS
that cpu controls scheduling/resources for the other cpus |
|
what is symetrical multiprocessing
|
form of tightly coupled where OS can be executed by any cpu, each cpu is responsible for its own dispatching and resources are shared by all cpus
|
|
what form of multiprocessing does intel use
|
master slave
|
|
what form of multiprocessing does amd use
|
SMP
|
|
what type of topology uses point to point
|
ring
|
|
what is a cluster
|
group of loosely coupled computers working together as a unit
|
|
what are the 2 types of clusters
|
shared disk
shared nothing |
|
ethernet is also known as
|
csma/cd
|
|
name the top 4 gen purpose registers
|
AX accumulator
BX base CX counter DX data |
|
what is AX register
|
temp storage, arith ops
|
|
what is BX register
|
temp storage, arith ops, base address pointer
|
|
in what register is the base address pointer
|
BX
|
|
what is the CX register
|
temp storage, arith ops, counter, index of array loops
|
|
what is the DX register
|
temp storage, combines with AX for multiplication/division & other arith ops
|
|
what are the bottom 4 gen registers
|
BP base pointer
SP stack pointer SI source index DI destination index |
|
what is the BP register
|
base pointer for the current stack
|
|
what is the SP register
|
pointer to current stack
|
|
what is the SI register
|
source index in array
|
|
what is the DI register
|
destination index in array
|
|
what are the 7 addressing modes
|
register, immediate, direct, register deffered addressing, base addressing, indexed addressing, base indexed addressing
|
|
x86 instructions are _ to __ bytes
|
1 to 15
|
|
what is the only required field in the x86 instruction
|
opcode
|
|
most x86 opcodes are _ byte long
|
1
|
|
what are the common flag instructions
|
carry, parity, auxillary carry, zero, sign, trap, interrupt enable, direction, overflow
|
|
what is the carry flag instruction
|
used by add/sub ops
|
|
what is the parity flag
|
set when result of op contains even number of bits
|
|
what is the aux carry flag
|
indicates carry or borrows during BCD arith
|
|
what is the zero flag
|
set if result of op is zero
|
|
what is the sign flag
|
set if the result is negative
|
|
what is the trap flag
|
used in debugging to halt cpu after each instruction
|
|
what is the interrupt enable flag
|
enable or disable hardware interrupts
|
|
what is the direction flag
|
define the direction of memory for string ops
|
|
what is the overflow flag
|
set if result of op is too big or small to fit in destination operand
|
|
floating point instructions were added to the processor starting with the ______ processor
|
80486DX
|
|
_____ and _____ instructions allow aperations like comparison and arithmatic on up to 8 numbers at a time
|
mmx and simd
|
|
the ____ address mode shows the source or destination is a register
|
register
|
|
the ___ address mode = the data source is part of the instructions
|
immediate
|
|
in ____ addressing the address of the source or destination is part of the instruction
|
direct
|
|
in _____ _____ _____ the address of the source or destination is found in a register
|
register deferred addressing
|
|
in ____ addressing the source or destination is found by adding the value in the displacement field of the instruction to a base address stored in a register
|
base addressing
|
|
in _____ addressing the address of the source or destination is calculated by adding a displacement specified in the instruction to the value in an index register
|
indexed
|
|
in ____ _____ addressing the address of the source or destination is calculated by adding both the value in the base reg and the index reg to the displacement in the instruction
|
base indexed
|
|
the ____ address points to somewhere within the memory allocated for the program
|
logical
|
|
the _____ address points to the map of the block of main memory
|
physical
|
|
___ mode uses 4 segment registers to point to blocks of memory allocated to a program
|
real
|
|
what is the real mode segment CS
|
code segment
|
|
what is the real mode segment DS
|
data segment
|
|
what is the real mode segment SS
|
stack segment
|
|
what real mode segments were added in the 80386 processor
|
FS GS
|
|
the ___ and ____ combine to point to the real mode address
|
segment register and logical address
|
|
what is added to the data segment register, combined with the logical address to find the 20 bit address
|
0 at the LSB
|
|
what is protected mode
|
instead of the segment register pointing to a block of memory, its reffered to as a selector register and points to an entry in a descriptor table for the base segment address
|
|
what did protected mode do?
|
allowed for multitasking, virtual storage, memory management which isolates OS and running tasks, and provided for efficient task switching
|
|
the isolation of the OS from running tasks was provided by _____
|
adding protection levels to the instruction sets
|
|
the OS runs at PL___
|
0
|
|
apps run at PL_
|
3
|
|
IA-64 itanium provides ___ 65 bit GP registers and ___ 80 bit floating point registers
|
128
|
|
which architecture has more gp regs?
|
power pc
|
|
what are the 7 categories for instructions in the powerpc
|
1 load/save
2 integer 3 floating point 4 flow control 5 processor control 6 memory control 7 vector |
|
powerPC cpu can be ___bit or ___ bit in size
|
32 or 64
|
|
the 32 bit powerPC has 32 bit gen and 32 bit address regs and can have up to __ bit virtual addressing
|
54
|
|
the 64 bit powerPC has 64 bit gp regs and address regs, and can address ___ bytes of memory
|
16 exabytes
|
|
the load/store instructions in a powerPC contain instructions for loading ___, ____, and ____ and ____.
|
bytes, halfwords, words, and floating point words and double words
|
|
the powerPC 64 bit implementation can load/store stings, multiple words of data in groups up to __ at a time
|
32
|
|
this instruction in the powerPC does the normal arith functions, and can execute ___ and ___ instruction.
|
integer, rotate and shift
|
|
this powerPC instruction set includes branch instructions for both ____ and ____ addressing instructions
|
flow control; relative and absolute addressing
|
|
memory addressing is used for ____, ____, ____ only
|
load store branch
|
|
this powerPC instruction set can provide different levels of capability, access and performance
|
processor control
|
|
memory control instructions give the powerPC programmer access to ____ memory, provides ____ instructions for setting and controlling various modes as well as ____ control for use with special I/O devices
|
cache memory, privileged instructions, external
|
|
the powerPC 7400 provides ___bit multifunctional vector execution unit
|
128
|
|
powerPC vector instructions can operate in ____ and provide integer and floating point arithmetic, logic functions, shifts, vector comparison, type conversion, packing and unpacking, and vector permutation capabilities
|
parallel
|
|
PowerPC memory addressing is used for load, store, branching only. Other instructions take their operands from _____ aka ____ mode.
|
fields within the instructions - immediate mode
|
|
the powerPC uses logical addressing. it uses 4 translation mechanisms for converting logical to physical:
|
ordinary
direct-store block addressing no translation |
|
what is ordinary translation logical addressing in a powerPC
|
divides the address into segment, page, offset
|
|
how is the powerPC segment (logical addressing) different to the intel segment
|
uses the segment like a super-page
|
|
PowerPC virtual storage divides memory into ___MB segments and divides segments into __KB pages.
|
256mb segments
4kb pages |
|
this powerPC logical address mode uses the segment table to perform segment translation, but the result is used directly with the remainder of the logical address to form a real address. also used in I/O addressing
|
direct-store translation
|
|
powerPC has ___ instructions
|
224
|
|
power PC word size
|
32 bits
|
|
this powerPC logical address mode provides means for mapping a block of logical addresses larger than a single page into a contiguous area of real memory
|
block addressing translation
|
|
the powerPC logical translation can be disabled, and its called
|
No Translation
|
|
powerPC has 2 levels of system access:
|
supervisor state and user (problem) state
|
|
in a powerPC, bits in the _____ _____ are used to set the state
|
system registers
|
|
PowerPC protects memory at the ____, _____, and ____ levels
|
segment, block and page
|
|
name the 3 z-series mainframes
|
s/360
s/370 s/390 |
|
the s/360 was introduced in ____
|
1964
|
|
the s/370 was introduced in ____
|
1970
|
|
the s370 added ____ _____ and support for ___ cpu's operating together
|
virtual storage; 2 cpu's
|
|
in 1981, ibm introduced the ____/__ design and added what
|
s370/XA; added more cpu's channel subsystem, and 31 bit address space
|
|
the s/390 has _____ __bit gp registers and __ floating point registers
|
16 64bit; 16 floating point
|
|
the s/390 has a ___bit program status word
|
128
|
|
the s/390 program status word contains the __, ___ for ___, an ___ key for cpu protection
|
program counter, mask bits for interrupts and an access key for cpu protection
|
|
all zseries instructions are ___, __, or __ bits in length
|
16, 32, 48
|
|
the length of zseries instructions are determined by ___
|
1st 2 bits in the opcode
|
|
in the zseries, there are __ different instruction formats depending on the operands and type of addressing used
|
18
|
|
zseries instructions operate between ____, ____ and ____, and ____ locations directly
|
registers, registers and memory, and memory
|
|
zseries divided the instructions into these 5 categories by type of operand (4 operands)
|
general, decimal, floating point, and control
|
|
in zseries, these instructions include data transfer,integer arith and logical ops, branches, shifts...
|
general
|
|
the special interupt ___ ___ is in the general instruction set in a zseries
|
supervisor call
|
|
these zseries instructions perform simple arith including rounding, editing, comparing, for packed decimals of varying length
|
decimal
|
|
operands for these zseries instructions are found in memory and do not use registers
|
decimal
|
|
these zseries instr include load store round normalize and compare floating point numbers and add, sub, div, mult, square root
|
floating point
|
|
the zseries floating point instructions work on __, __, and ___ bit formats
|
32, 64, 128
|
|
zseries ____ instructions are privileged and operate flags in the PSW
|
control
|
|
zseries defines 4 types of addressing operands:
|
immediate, register, storage, storage indexed
|
|
zseries immediate data is found in the ____ field of the instruction
|
immediate
|
|
this zseries address mode is found by adding the base register, b field of the instruction and the displacement field of the instruction
|
storage
|
|
this zseries address mode is similar to storage addressing, with the addition of an index value
|
indexed storage
|
|
the zseries index value is stored in a register indicated by an __ field in the instruction
|
x field
|
|
does the zseries use logical addressing?
|
yes, using a segment and page lookup table
|
|
zseries cpu can operate in these 2 modes
|
supervisor or problem state
|
|
zseries cpu provides storage access protection at the ____ ___, ____, and ____ levels
|
address space, segment and page levels
|
|
zseries address spaces can be completely isolated from each other
|
true
|
|
in zseries, the ____ stored in the PSW is used to compare against the ____ info stored for each page in order to control access to memory
|
access key
|
|
API stands for
|
application programming interface
|
|
API does what
|
provides interface with system, files, other programs
|
|
define OS
|
collection of computer programs that integrate hardware and make resources available to user and allows productive timely, efficiency
|
|
two names for starting a computer
|
bootstrapping and IPL (initial program load)
|
|
single-user single tasking OS
|
DOS
|
|
single user multi-tasking OS
|
win/home
|
|
multi user multitasking OS/computer
|
mainframe/epcidic
|
|
distributed system type
|
cluster or google
|
|
embedded system type
|
car/cell/low-power OS
|
|
real time system type
|
batch jobs
|
|
part of the OS that contains routines to handle interrupts manage resources and in some OS's will accept user commands
|
kernel
|
|
what are the 3 main memory resident components of MSDOS
|
1 cmd shell
2 I/O routines for each device connected 3 file mgt system |
|
bios is contained in this type of memory
|
ROM/non-volitile
|
|
3 files required by MSDOS
|
io.sys command.com msdos.sys
|
|
MSDOS supports only ____ mode addressing
|
real
|
|
a ____ is considered the standard unit of work within a computer system
|
process
|
|
processes include the program running and _____
|
the resources assigned to it
|
|
the process control mgt keeps track of each process in ___, determines the state of each process and keeps track of the processes files, register info, and memory.
|
memory
|
|
what is the purpose of the memory manager
|
load programs into memory and assign the memory it needs to execute
|
|
the memory mgr has 3 tasks:
|
1 keep track of memory
2 maintain queues 3 allocate/deallocate space |
|
what are threads
|
mini-processes
|
|
each thread can have its own context
|
true
|
|
each thread cant have its own stack
|
false
|
|
what are the 5 process states
|
1 new
2 ready 3 blocked 4 running 5 terminated |
|
program scheduling is aka _____
|
dispatcher
|
|
the dispatcher can be _____ or _____
|
preemptive or non-preemptive
|
|
explain non-preemptive dispatching
|
dispatcher takes control of the current running process due to blocked i/o or some other malfunction
|
|
explain preemptive dispatching
|
multitasking that uses the clock cycle to preempt the running program and make a fresh decision
|
|
dispatchers prevent what
|
starvation
|
|
starvation can happen in this I/O mode
|
SJF - shortest job first
|
|
which scheduling technique manages i/o and then goes back to FIFO
|
priority scheduling
|
|
preemptive dispatching in its simplest forms
|
round robin
|
|
name 2 things about multilevel feedback queue
|
favors short jobs
i/o bound jobs each level assigns more cpu time |
|
what service handles context switching
|
dispatcher
|
|
simplest (non-preemptive) dispatching where starvation is impossible
|
FIFO
|
|
if a process has been running a long time this dispatcher scheduling technique allows other processes access
|
dynamic priority scheduling
|
|
before virtual storage, the memory mgr divided memory into
|
partitions
|
|
name the two types of memory manager partitioning
|
fixed and variable partitioning
|
|
term for when memory manager overwrites portions of memory with new code
|
overlays
|
|
windows uses a page file, unix its called
|
swap partition
|
|
system performs page swapping only when required as result of page fault
|
demand paging
|
|
system attempts to anticipate paging needs
|
prepaging
|
|
tendency of a process to execute in small areas of memory - outside where the main body of the program executes
|
locality
|
|
pages shared among different processes
|
page sharing
|
|
repeated page swapping
|
thrashing
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to improve performance for page table lookups, most systems use a small amount of special memory called _______ ______
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associative memory
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ability of the OS to protect process's pages from being accessed by another program
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process separation
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endianess where MSB is on the left side
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big endian
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endianess where MSB on the right
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little endian
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name the 2 types of hard drive free space management
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bitmap and linked list
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file management system that stores data about files... attributes
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metadata layer
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name the 2 types of directory/file name structures
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tree and acyclic
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powerPC cpu and memory instructions are considered _____
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priviliged
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two types of computer clusters
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shared disk and shared nothing
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name the 4 parts of a hard drive)
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sectors, tracks, blocks (512b) cylinders
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hard drive velocity where the bits on each track are the same
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constant angular velocity
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which computer type, powerPC or x86 uses big endianess
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PowerPC
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what sector is the MBR on?
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0
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generalization representation of a file tree
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acyclic graph
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