Use LEFT and RIGHT arrow keys to navigate between flashcards;
Use UP and DOWN arrow keys to flip the card;
H to show hint;
A reads text to speech;
71 Cards in this Set
- Front
- Back
- 3rd side (hint)
|
6 code combinations that are invalid in the 8421 BCD code |
1010, 1011, 1100, 1101, 1110 and 1111 |
|
|
|
BCD addition/subtraction rule |
If a 4-bit sum/difference is greater than 9 , or if a carry/borrow out of the 4-bit group is generated , it is an invalid result. Therefore, add/subtract (0110) 6 to/from the 4-bit sum/difference in order to skip the six invalid states and return the code to 8421 BCD. |
|
|
|
BCD more info |
If more than one group (i.e. digit aka 4 bit code of a longer number) is invalid , add 6 to all those groups. Even if after carry generation, the code looks like a valid bcd, still you have to add 6. |
|
|
|
BCD subtraction info |
Subtract 0110 from all invalid codes or if a borrow is generated. |
|
|
|
Gray Code |
Unweighted Not an arithmetic code (no specific weighta assigned to the bit positions) It exhibits only a single bit change from one code word to the next in sequence. Important application : Shaft position encoders. The single bit change characteristic of the gray code minimises the chance of error. |
|
|
|
Binary to Grey code |
Write down the first bit from LHS and then in binary form do first bit + second bit = second gray bit (from LHS) and so on. (Addition without carry i.e. 1+1=0 aka XOR) |
|
|
|
Gray Code to Binary |
Write first bit from left as it is. Then do first binary bit + second grey bit = second binary bit , second binary bit + third grey bit = third binary bit and so on. (All from LHS) |
|
|
|
Parity method |
Means for bit error detection A parity bit is attached to a group of bits to make the total number of 1s in a group always even (Even parity) or always odd (Odd parity). |
|
|
|
Hamming Codes |
Error correct codes : employed in information transmission In this each group of binary information(of m bits), k number of parity bits(p1, p2, p3,.... pk) are inserted at (2^k-1)th positions from left, so that to make a total (m+k)bit code. Parity checks are performed for k times and error word is formed for locating the error bits. |
|
|
|
7 bit hamming code |
P1 P2 D3 P4 D5 D6 D7 P1 - 1 , 3 , 5 , 7 P2 - 2 , 3 , 6 , 7 P3 - 4 , 5 , 6 , 7 For getting C1, C2 and C3 respectively. Then C3C2C1 is the binary code for the error bit position (found in the original number from LEFT HAND SIDE) |
|
|
|
Half Adder |
Accepts two single bit binary numbers on its inputs and produces two binary numbers on its output - Sum(XOR i.e. addition without carry) and Carry(AND i.e. the carry left after sum aka '.'). |
|
|
|
Full Adder |
Accepts two single-bit binary numbers and an input carry on its input and generates two binary numbers on its output - Sum and Carry Min-terms : Sum = (1,2,4,7) Carry = (3,5,6,7) |
|
|
|
Full Adder |
Accepts two single-bit binary numbers and an input carry on its input and generates two binary numbers on its output - Sum and Carry Min-terms : Sum = (1,2,4,7) Carry = (3,5,6,7) |
|
|
|
Difference between full adder and half adder |
Full adder accepts an input carry (Cin) |
|
|
|
Maxterms |
POS form (A+B)(A+B)... form 0 means A , 1 means A' Capital M |
|
|
|
Minterms |
SOP AB+AB .... form 1 means A and 0 means A' Sigma and small m |
|
|
|
Look ahead carry Adder |
Speeds up the process by eliminating the ripple carry delay. It examines all the input bits simultaneously and also generates carry-in bits for all the stages (full-adders) simultaneously. For this a carry can be produced when : 1. Both bits Ai and Bi are 1 2. One of the two bits is 1 and the carry-in(from previous stage) is 1 |
|
|
|
4 bit look agead carry adder |
Each sum requires 2 XOR gates. The carries are propagated through the look-ahead carry generator which requires two gate-level delay provided that all P's and G's are available. Thus the outputs from S2 to S4 have equal delay time i.e. 4 gate-levels instead of 8 gate-levels delay in case of ripple carry adder. |
|
|
|
Ripple carry adder |
One in which the carry output of each full-adder is connected to the carry input of the next higher-order stage (a stage is one full-adder). The sum and output carry of any stage cannot be produced until the input carry occurs , this causes delay in the process. |
|
|
|
4-bit parallel Adder IC |
IC : 74HC283 and 74LS293 By using multiple 4-bit parallel adders the addition of higher-bit numbers can be performed. The output carry from least significant nibble (a group of 4 bits) is supplied to the input carry to the higher significant nibble adder. |
|
|
|
4-Bit parallel adder |
A basic 4-bit parallel adder is implemented with four full-adder stages. The LSBs (A1 and B1) in each number being added go into the right-most full-adder; the higher order bits are applied to the successively higher order adders, with the MSBs (A4 and B4) in each number being applied to the left-most adder. The carry output of each adder is connected to the cardy input of the next higher-order adder . These are called internal carries. |
|
|
|
Parallel binary Adder |
Two or more full adders are connected to form parallel binary adders to add binary numbers with more than one bit. When one binary number is added to another, each column generates a sum bit and a 1 or 0 carry bit to the next column to the left. For n-bit number, n full adders are used. The output of each adder is connected to the carry input of the next higher-order adder. |
|
|
|
MSB Lsb in BPA |
Either a half adder can be used for the least significant position or the carry input of a full-adder can be made 0 (grounded) because there is not carry input to the least significant bit position. Also, the carry output from the leftmost full adder becomes the most significant bit (MSB) in the sum. |
|
|
|
Half-Subtractor |
It accepts two single-bit binary numbers on its inputs(A and B) and produces two binary numbers on its outputs - Difference (D) and Borrow (Bout) (if any borrow has been tKen away, it is 1 otherwise 0) |
|
|
|
Full-subtractor |
It accepts two single-bit binary numbers and a borrow (in) on its input and generates two binary numbers on its output - Difference and borrow (out). |
|
|
|
Difference between full subtractor and half subtractor |
The full subtractor also considers the borrow taken away by the lower significant bit. |
|
|
|
4 bit adder/subtractor |
The subtraction of binary numbers can be done most conviniently by means of complements. The subtraction A-B can be done by taking the 2's complement of B and adding it to A. The 2's complement can be obtained by taking the 1's complement and adding one to the least significant pair of bits. The 1's complement can be implemented with inverters and a one can be added to the sum through the input carry. |
|
|
|
Representation of signed numbers |
1. Sign-magnitude form - leftmost bit represents the sign , rest if the bits represent the magnitude. 2. 1's complement form - positive numbers as normal binary, negative numbers are represented as their 1's complement (complement all the bits) 3. 2's complement form - 1's complement + 1 (going from right to left copy all the bits from right side till first 1 and then complement the rest of the bits)
|
|
|
|
Boolean axioms |
0+0 = 0 0+1 = 1 1+0 = 1 1+1 = 1 0.0 =0 0.1 = 0 1.0 = 0 1.1 = 1 0' = 1 1' = 0 |
|
|
|
AND law |
A.0 = 0 A.1 = A |
|
|
|
OR law |
A + 0 = A A + 1 = 1 |
|
|
|
Commutative law |
A + B = B + A A.B = B.A |
|
|
|
Associative law |
A + (B +C) = (A+B)+C (A.B).C = A(B.C) = (A.C).B |
|
|
|
Distributive law |
A(B+C) = A.B + A.C A+BC = (A+B)(A+C) |
|
|
|
Identity law |
A.1 = A A + 0 = A |
|
|
|
De-morgan's law |
(A+B)' = A'.B' (A.B)' = A' + B' |
|
|
|
Redundant literal rule |
A + A'B = A + B A(A' + B) = A.B A + A'BCD = A + BCD |
|
|
|
Consensus Theorem |
AB + A'C + BC = AB + A'C (A+B)(A'+C)(B+C) = (A+B)(A'+C) |
|
|
|
BCD |
Also called 8421 code. Minimum requirement for a binary coded decimal system is that it should be 4-bit. Addition of weights must be at least 9. |
|
|
|
Weightage coding systems |
Thise coding systems in which individual bit positions can be assigned particular weights. Eg. 8421,5421, 542-1. |
|
|
|
Non-weightage coding systems |
Eg. Gray codes, XS-3 codes. |
|
|
|
Sequential code |
The binary representation of successive numbers differ by 1. Eg. 8421, XS-3 |
|
|
|
Reflective code |
In a n-bit system, the code words of last n-1 bits of the number from 2^n-1 to (2^n)-1 are the reflection of last n-1 bits of number from 2^(n-1)-1 to 0 respectively. Eg. Gray code |
|
|
|
Positively weighted and negatively weighted codes |
If any portion has negative weight. Eg. 542-1 Eg. Of positive weighted : 8421, 5421, etc. |
|
|
|
Cyclic code |
In cyclic code, the binary representation of successive numbers differ by 1 bit position. Eg. Gray code. |
|
|
|
Self-complementary code |
Those codes in which 9's complement of a number can be found out by simply complementing all the bit positions. Eg. Excess-3 |
|
|
|
Error detecting code |
By just looking at the code, The reciever will be able to detect the error and ask the sender to send the message again. Eg. 1 bit parity coding. |
|
|
|
Error correcting code |
By just looking at the code, the reciever will be able to detect the error bit positions and subsequently will be able to correct the code. |
|
|
|
ADC AND DAC Real world signals |
Analog quantity i.e. continuous in time Quantified at every single instant of time. |
|
|
|
Digital format of signals |
Digital processing, torage and transfer , etc. |
|
|
|
Analog to Digital conversion (ADC) |
A continuously varying analog signal into a series of discrete levls. This series of levels follows the variations of the analog signal and resembles a staircase. The process of changing the original analog signal to the "stairstep" approximation is accomplished by a sample and hold circuit. |
|
|
|
Sampling |
Process of taking a sufficient number of discrete values at points on a waveform that will define the shape of the waveform. More samples = more accuracy Converts an analog signal into a series of impulses, each representing the amplitude of the signal at a given instant in time. |
|
|
|
Before sampling |
A signal is passed through a low-pass filter (anti-aliasing filter) to eliminate harmonic frequencies ablove a certain value as determined by the Nyquist frequency. |
|
|
|
Sampling Theorem |
States that in order to represent an analog signal, the sampling frequency fsample, must be at least twice the highest frequency component fa(max) of the original analog signal. |
|
|
|
Quantization |
The process of converting an analog value to a code is called quantization. converts each sampled value of the analog signal to a binary code. More bits - more accurate. |
|
|
|
ADC parameters |
1. Resolution - no. Of bits 2. Throughput - sampling rate an adc can handle in units of samples per second (sps). |
|
|
|
Resolution (step size) |
The resolution of DAC is defined as the smallest change that can occur in an analog output corresponding to a change in the digital input. Equal to weight of lsb |
|
|
|
Operational Amplifier |
Op-amp is a linear amplifier that has two inputs (inverting and non-inverting) and one output. It has a very high voltage gain and a very highinput impedance, as well as very low output impedance. |
|
|
|
Dac |
Process of converting a value represented in digital code (such as straight binary or bcd) into a voltage or current proportional to the digital value. |
|
|
|
Binary weighted resistor dac |
1. One resistor or current source for each bit of the dac connected to a summing point. 2. Precise voltages or currents sum to correct output values 3. Fastest conversion, poor accuracy (high precision required for each V or I) 4. High precision resistors and current sources are expensive (:. Limited to 8-bit resolution or less) 5. Named (since r values are wted acc with bin wts) 6. Input in volts weighted in the summing amplifiers to produce corresponding analog value 7. Unsatisfactory for higher no. Of bits |
|
|
|
R-2R ladder dac |
Binary weighted dac Uses a repeating cascaded structure of resistors of values R and 2R. Improved precision (relative ease of producing equal valued matched resistors (current sources)) Wide convertors perform slowly due to increasing large time constants for each R-2R link. |
|
|
|
Flash / Simultaneous / parallel comparator type analog-to-digital converter |
1. Fasted ADC, speed is being limited only in comparator and gate propagation delay. 2. No. Of comparators required = 2^n - 1 3. No. Of resistors = 2^n For n bits. |
|
|
|
Successive-Approximation type ADC |
Maximum no. Of clock pulses required is N Ct = NTc |
Ct = conversion time Tc = time period of clock cycle N = N-bit adc |
|
|
Synchronous counter |
One in which all the flip-flops in the countee are clocked at the same time by a common clock pulse. |
|
|
|
Popular ICs of logic families |
TTL OR T^2L : Transistor-transistor logic ECL : Emitter Coupled Logic CMOS : Complementary metal-oxide semiconductor |
|
|
|
Operational properties of logic families |
1. Voltage levels 2. Noise immunity 3. Power dissipation 4. Fan-in & fan-out 5. Propagation delay time |
|
|
|
Noise immunity |
Ability to tolerate a certain amount of unwanted voltage fluctuations on its inouts without changing its output state (in order to not be adversely affected by noise). |
|
|
|
Noise margin |
Measure of a circuit's noise immunity (in volts). Two values : VNH : high level noise margin VNL : low level noise margin |
|
|
|
Loading |
When the output of a logic gate is connected to one or more inputs of other gates, a load on the driving gates is created. |
|
|
|
Fan-out |
Limit to the number of load gate inpits that a given gate can drive. Expressed as unit loads One gate input - unit load to a driving gatw of the same logic family.1 |
|
|
|
Propagation delay |
A change in the output level always occurs after a short time, called the propagation delay time, later than the change in the input level that caused it. tPD = tPLH + tPLH/2 |
|
