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86 Cards in this Set
- Front
- Back
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Network |
Group of machines connected together, often by one cable |
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Circuit vs packet switched network |
Circuit: Formed between 2 machines to allow communication Packet: Messages broken down into packets and sent interleaved. More efficient |
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Network layer model |
7. Application 6. Presentation 5. Session 4. Transport 3. Network 2. Data link 1. Physical |
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1. Physical layer |
How data travels on a physical level e.g. ethernet/wifi |
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2. Data link layer |
How data is formatted, who packet is for, etc. e.g. ethernet/wifi, PPP |
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3. Network layer |
Deals with packet forwarding across network
e.g. IPv4, IPv6 |
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Get around machines on different networks having same no.s by...
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...assigning a number for each network eg. 1.2 is network 1, machine 2. |
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IP Address classes |
Class A: 1.x.x.x to 127.x.x.x Big companies Class B: 128.0.x.x to 191.255.x.x Class C: 192.0.0.x to 223.255.255.x Class D: 224.0.0.0 to 239.255.255.255 Class E: 240.0.0.0 to 255.255.255.255 |
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Classless inter-domain routing |
Avoid space running out on IPv4 by breaking down any address into any no. of bits. Written eg. 10.0.0.1/8 to represent 8 bits starting at the given address |
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IPv4 vs IPv6 |
IPv4 uses 64 bits - getting full IPv6 written in hex, using 128 bits. Designed to solve this. |
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Configurable vs Dynamic IP address allocation |
Configurable: Specify address yourself Dynamic: Allocated automatically using Dynamic Host Configuration Protocol (DHCP) and Stateless Address Autoconfiguration (SLAAC) |
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Address resolution protocol |
Way of finding out if IP address is on same local network as machine. If it is, send directly. If not, send away from local network |
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DNS lookup process e.g. belgian.waffles.co.uk |
.uk is top level domain, held by a few machines (8 for .uk) These machines then provide more machines with IP addresses for .co layer Keep going until waffles.co.uk reached This provides the full IP address for belgian.waffles.co.uk |
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DNS Servers: Authoritative vs Recursive vs Caching |
Authoritative: Hold answer to query Recursive: Perform search to get answer Caching: Store answer for faster response (like a cache) |
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4. Transport layer |
End to end communication
e.g. TCP |
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5. Session layer |
Manage session between end-user applications processes e.g. SPDY |
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6. Presentation layer |
How data is presented e.g. HTML, CSS, GIF, JPG, MP3 |
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7. Application layer |
User interface e.g. HTTP, POP3 |
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Switches in series vs Switches in parallel |
In series = AND gate In parallel = OR gate |
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Logic gate precedence e.g. A+B.~C |
1. NOT 2. AND 3. OR A+B.~C = A+(B.(~C)) |
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A+0= A+1= A+A= A+~A= A.0= A.1= A.A= A.~A= ~~A= |
A+0=A A+1=1 A+A=A A+~A=1 A.0=0 A.1=A A.A=A A.~A=0 ~~A=A |
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A+B= (A+B)+C= (A.B)+(A.C)= A.B= (A.B).C= (A+B).(A+C)= |
A+B=B+A (A+B)+C=A+(B+C) (A.B)+(A.C)=A.(B+C) A.B=B.A (A.B).C=A.(B.C) (A+B).(A+C)=A+(B.C) |
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De Morgan's Theorem |
~(A.B)=~A+~B ~(A+B)=~A.~B |
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Decimal to Binary |
Divide by 2 again and again and keep remainder each time New no. is made up of remainders, from last to first |
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Half-adder vs Full adder |
Half-adder adds 2 bits Full-adder adds 3 bits Carry and sum output can be drawn as result of gates For half-adder, carry is AND, sum is XOR |
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Ripple Carry Adder |
Adds 2 multi-bit no.s Right to left Series of full adders, adding carry in, and relevant bits of two numbers |
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Four negative no. representations |
Sign and Magnitude One's complement Excess-n Two's complement |
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Sign and magnitude no.s and subtraction |
Top bit represents sign (0 +ive, 1 -ive) Find and subtract no. with larger magnitude, and adjust signs |
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Excess-n no.s |
Add n to no.s, so -n = 0000 |
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One's Complement no.s and subtraction |
Top bit gives sign -ive values inverted Subtract by adding -ive, and adding carry bit |
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Two's Complement no.s |
Top bit gives sign -ive values inverted Then add one if -ive Subtract by adding -ve, and throw away carry |
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Combinatorial vs Sequential Logic |
Combinatorial: Output a combo of input values Sequential: Has a time component, reliant on clock, depends also on sequence of previous inputs |
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CPU (and logic type) |
Central Processing Unit Takes instructions and executes them Combinatorial and sequential logic |
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ALU (and logic type) |
Arithmetic and Logic Unit Performs all arithmetic and logic operations for CPU Combinatorial logic only |
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Criteria for selecting what ALU functions should exist |
Minimise amount of logic needed to perform tasks Fewer logic gates Fewer transistors = cheaper Less propogation delay = faster |
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MUX gate (right way around) |
sel=0 => out=A sel=1 => out=B |
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Von Neumann Model |
Memory CPU Input and Output Address bus Input to CPU (CPU to mem) Data bus CPU to output (both ways) |
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Three CPU components |
ALU (heart) Registers (store data) Control logic (manipulates ALU using data received to perform operations) |
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Von Neumann Bottleneck |
CPU can't fetch an instruction and modify data simultaneously |
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Register |
Stores info, output remains the same until told otherwise Input load decides whether to update output load(t-1) => out(t)=in(t-1) else out(t)=out(t-1) |
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Control logic |
Generates a series of control signals which control movement of data through the data path |
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Data Path |
Path through which the data travels to perform processing |
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NOT Oscillator |
NOT gate creates an output, which can be fed back into itself |
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SR Latch |
Inputs R and S, start all 0 Input into separate NOR gates, with output leading into each other, as well as Q and ~Q respectively S high => Q high S then low => Q still high Circuit remembers if it has been set or reset R high => Q low R then low => Q still low Q has reset to 0 |
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D Latch/Flip Flop. Description and Difference |
Like SR Latch Data input D and Clock input CLK CLK high => D goes to output CLK low => output remains as prev Flip Flop, unlike D latch, stores input when CLK goes low to high out(t)=in(t-1) |
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How to store multiple bits with a flip flop |
Use multiple flip flops! One for each bit Use same CLK input so all update simultaneously |
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Clock |
Oscillates between 0 and 1 at a fixed frequency |
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Clocked DFF |
Keeps the same state throughout the entire clock oscillation, regardless of change in input, and updates on every low to high clock transition |
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Read from RAM |
Put register outputs into multi-way Mux to get required output |
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Write from RAM |
Use a multi-way DMux to direct the input into the correct register |
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State Machine |
Machine travels through a series of states to dictate what it does |
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Finite State Automata Rules |
One start state Can have many end states Transitions between states depend on certain conditions being met (or not) |
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Simplifying Finite State Automata (why and how) |
Fewer states => logic is simpler Combine states if they can be portrayed similiarly |
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Represent FSA in computer |
Use n flip flops to store state, where 2^n >= no. of states |
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Use FSA for Control Logic |
Generate a series of outputs to control movement of data through data path |
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Moore vs Mealy Machine |
Moore Machine - output depends on current state only Mealy Machine - output depends on state and input |
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Reset Pin (FSA) |
aka Reset Logic Used to return to start state when specific input provided |
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Two pieces of software required for active connection |
Client and server |
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Berkeley sockets treat everything as a... |
...file |
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Client side connection order of events |
socket() - create connection connect() - connect to server, provide IP address and port to connect to read()/write() - as it says close() - close connection |
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Server side connection order of events |
socket() - create connection bind() - to a given port listen() - API provides queue of potential connections accept() - establish connection when it happens read()/write() - as it says close() - close connection |
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Big vs Little Endian |
Big endian - addresses stored Most sig bit to least sig bit Little endian - other way around |
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Problems with endianness over networks |
Not consistent - have to convert when using addresses to guarantee it is correct Internet standardises on big, many CPUs little |
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Machine Code |
Gateway between hardware and software - turns instructions into physical operations |
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6502 Components |
Accumulator (A) - main register, what's being operated on X and Y - temp storage, transfer, etc. |
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Opcode assignment |
All opcode instructions assigned using a unique binary no. Use a pattern to simplify their implementation - group together in rows and columns by having bits the same eg. aaabbb01 aaa - drive mem access (instruction) bbb - drive ALU (addressing mode) 01 - show it is an instruction being processed through ALU |
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Destination Accumulator - steps taken to carry out opcode instruction |
1. Load register with acc to feed ALU input A 2. Load register with value from mem to feed ALU input B 3. Set ALU ftn and store ALU output in acc |
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Decode opcode instruction |
First three bits have memory access Next three bits drive ALU |
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CPU State Machine - states |
0 - Fetch instruction into instruction register 1 - Load acc value into ALU A register 2- Load mem value into ALU B register 3 - Calculate value and store result in acc |
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Flip Flop State Machine (get direction right) |
All connected in a loop, with output values between each one Every time clock ticks, the output value cycles around in the direction of the connection State is given as the appropriate output value |
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CPU State Machine - design |
Flip Flop state machine with Mux between each one. Mux input A is output of prev flip flop Mux input B is 1 if correct state, 0 otherwise |
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ALU Status Flags - 4 flags |
Negative flag - ALU bit 7 Zero flag - NOR ALU bits Carry flag - carryOut of ALU Overflow flag - Is overflow generated? |
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6502 Branch Instruction |
Of form xxy10000 xx is status flag to base on (out of the 4) Compare with value in y using XNOR If equal, take the branch Otherwise, don't |
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Accessing various bits - what must they include? How are they arranged? |
Must include RAM, ROM, I/O Arrangement can include spaces if it helps place things more readably |
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Output Enable (OE) |
Control whether chip is active OE controls whether data bus is in high-impedence state i.e. equivalent to chip being disconnected from data bus |
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Chip Select (CS) |
Generate a chip select logic signal for each chip to select chip Chip will only be selected if address on address bus is in correct range |
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Simplify chip addresses for selection |
Will need to select chips using logic gates with all the bits. Simplify by allocating chips in locations where as few logic gates as possible will be required to only select that chip |
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Operating System components (4) |
Kernel - the heart and soul Filesystem - where files are stored Userland - Parts outside kernel e.g. __init__ Shell - for human interaction with OS |
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CPU Privilege - 2 most common modes |
Supervisor mode (ring 0) - access any bit of mem, hardware, do anything User mode (ring 3) - only access certain instructions |
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User Mode |
Only access certain instructions Allow OS to restrict what programs can do Programs can't directly access hardware unless OS gives permission |
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System Call |
SWI Switch CPU from user mode to supervisor mode, and start executing instruction in a defined place, under the control of the OS, rather than the program, before returning to user mode |
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init Process |
Start in userland Initialise any tty's (terminals) by reading file /etc/ttys Runs process getty to handle each tty getty runs login prompt on each terminal init then runs shell script to start everything else off |
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Resource management - what if multiple processes running on CPU? |
OS must take control of who has access to what mem Program asks OS for a block of mem to use of given size. OS returns address of some free mem When program finished with mem, it returns it to OS, freed. |
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What if no mem left? |
OS can just tell program 'no' Or, use virtual memory - temporarily swap another process's mem out of RAM to disk, until the other process needs it again |
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Memory Management Unit |
Helps with transfer of mem between RAM and disk, when space is short |
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Paging - what is it? What if mem is full? |
Memory in hardware broken up into chunks called pages. Mem required for two processes interleaved with one another If mem full and process A needs some mem, OS can temporarily move one of process B's pages to disk. If process B needs it, it can ask for it back |
