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24 Cards in this Set

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What is the first step of the fetch-execute cycle?

The address of the next instruction is held in the PC and copied to the MAR

What is the second step of the fetch-execute cycle?

This address is decoded and the address bus set so the instruction can be fetched into MBR

What is the third step of the fetch-execute cycle?

The PC is incremented

What is the fourth step of the fetch-execute cycle?

Contents of MBR is copied to IR

What is the fifth step of the fetch-execute cycle?

The instruction is decoded and then executed

What is the sixth step of the fetch-execute cycle?

Data to be operated on is held in the ACC

What is the seventh step of the fetch-execute cycle?

The result from the operation is held in the ACC

What is an interrupt?

A signal from some device/source seeking the attention of the processor

Interrupts can be enabled or disabled during an instruction or set of instructions. True or False?

True

If interrupts are enabled then the program is suspended to allow the interrupt to be serviced. True or False?

True

When the interrupt has finished, what happens?

It goes back to the previous task

How does the CPU keep track of where it was before the interrupt?

It writes the address of an interrupted task to a special register known as a stack

Interrupts have don't have priority levels. True or False?

False. They do have different priority levels

What might happen if the CPU is busy and there is a low priority interrupt?

The CPU might temporarily ignore them but would respond immediately to a high priority one like a disk error message

What are the 4 different types of interrupts?

Program, timer, I/O interrupts and hardware failure

What are program interrupts?

They are generated by something that has happened in the program, i.e. in the execution of an instruction. An example would be attempting to divide by zero

What are timer interrupts?

They are generated by a timer within the processor - enables O.S. to perform certain functions at regular intervals. In a multi-user system, the O.S. will pass control of the processor to each user in turn

What are I/O interrupts?

They are generated by an input-output controller, e.g. a keyboard controller. May signal that an operation has been completed, or that a device is ready, or that an error has occurred

What is the order of priority between timer, program, hardware failure and I/O?

Hardware failure = 1


Program = 2


Timer = 3


I/O = 4

What is the ISR?

Interrupt Service Routine

When is the ISR run?

When the interrupt is called, the processor runs it

How does the vectored interrupt mechanism work?

The interrupting device supplies an offset (number). This is added to the base address which gives the address of the interrupt service routine (ISR) which is to be executed

How many steps are there in the interrupt service routine?

10


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