2.1.2 Structured Design and challenges
The Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway for saving microchip area by minimizing the interconnect fabrics area. This was attained by continuous research of rectangular macro blocks which can be interconnected using wiring by abutment. The Structured VLSI design had been widespread in the initial 1980s, but lost its effect later since the advent of placement and routing tools wasting a lot of region by routing, which is abided because of the progress of Moore's Law.
Moore's Law
Moore's law gives a long-term trend in the history of totaling hardware. The figure of transistors that can be located inexpensively on an integrated circuit IC doubles approximately …show more content…
These tools work self-possessed in a design flow that chip designers use to design and scrutinize all-inclusive semiconductor chips.1981 marks the establishment of EDA as an industry. Since many years, the larger electronic companies, such as Hewlett Packard, Tektronix, and Intel, had trailed EDA within. In the year 1981, managers and developers gyrated out of these companies to concentrate on EDA as a business. The Daisy Systems, Mentor Graphics, and Valid Logic Systems were all founded around this time, and mutually bring up to as …show more content…
Fig 3.2 Basic Simulation Flow
• Creating the Working Library
In ModelSim, all the designs are compiled into a library. We typically start a new Simulation in ModelSim by creating a working library called "work," which is the default library name used by the compiler as the default destination for compiled design units.
• Compiling our Design
After creating the working library, we compile our design units into it. The ModelSim library format is compatible across all supported platforms. We can simulate our design on any platform without having to recompile our design.
• Loading the Simulator with our Design and then Running the Simulation
With the design compiled, we load the simulator with our design by invoking the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). Assuming the design loads successfully, the simulation time is set to zero, and we enter a run command to begin simulation.
• Debugging our Results
If we don’t get the results we expect, we use ModelSim’s robust debugging Environment to track down the cause of the problem.
3.2.3 PROJECT
The Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway for saving microchip area by minimizing the interconnect fabrics area. This was attained by continuous research of rectangular macro blocks which can be interconnected using wiring by abutment. The Structured VLSI design had been widespread in the initial 1980s, but lost its effect later since the advent of placement and routing tools wasting a lot of region by routing, which is abided because of the progress of Moore's Law.
Moore's Law
Moore's law gives a long-term trend in the history of totaling hardware. The figure of transistors that can be located inexpensively on an integrated circuit IC doubles approximately …show more content…
These tools work self-possessed in a design flow that chip designers use to design and scrutinize all-inclusive semiconductor chips.1981 marks the establishment of EDA as an industry. Since many years, the larger electronic companies, such as Hewlett Packard, Tektronix, and Intel, had trailed EDA within. In the year 1981, managers and developers gyrated out of these companies to concentrate on EDA as a business. The Daisy Systems, Mentor Graphics, and Valid Logic Systems were all founded around this time, and mutually bring up to as …show more content…
Fig 3.2 Basic Simulation Flow
• Creating the Working Library
In ModelSim, all the designs are compiled into a library. We typically start a new Simulation in ModelSim by creating a working library called "work," which is the default library name used by the compiler as the default destination for compiled design units.
• Compiling our Design
After creating the working library, we compile our design units into it. The ModelSim library format is compatible across all supported platforms. We can simulate our design on any platform without having to recompile our design.
• Loading the Simulator with our Design and then Running the Simulation
With the design compiled, we load the simulator with our design by invoking the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). Assuming the design loads successfully, the simulation time is set to zero, and we enter a run command to begin simulation.
• Debugging our Results
If we don’t get the results we expect, we use ModelSim’s robust debugging Environment to track down the cause of the problem.
3.2.3 PROJECT