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25 Cards in this Set
- Front
- Back
Single Cycle Design
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Fetch, Decode and Execute each instruction in one clock cycle
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Who invented pipeling
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ILLIAC II, a project at UIUC publishes first (1958)
– IBM Stretch implements first (1960 |
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What does piplining do to throughput
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Improves
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What does piplining due to latency
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not reduced
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structural hazards
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attempt to use the same resource by two
different instructions at the same time |
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data hazards
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attempt to use data before it is read
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control hazards
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attempt to make a decision about program
control flow before the condition has been evaluated and the new PC target address calculate |
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cache
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small but fast memory
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principle of locality
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present the
user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology |
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Temporal Localit
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If a memory location is referenced then it will tend to be
referenced again soo |
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Spatial Locality
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If a memory location is referenced, the locations with nearby
addresses will tend to be referenced soon |
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block (line)
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the minimum unit of information that is
present (or not) in a cach |
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hit rate
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the fraction of memory accesses found in a level
of the memory hierarch |
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miss rate
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the fraction of memory accesses not found in a
level of the memory hierarchy ⇒ 1 - (Hit Rate |
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hit time
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Time to access that level which consists of
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miss penalty
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Time to replace a block in that level with the
corresponding block from a lower level which consists of |
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write-through
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always write the data into both the cache block and the next level in
the memory hierarch |
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compulsory
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cold start or process migration, first
reference |
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capacity
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Cache cannot contain all blocks accessed by the progra
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Spatial Locality
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If a memory location is referenced, the locations with nearby
addresses will tend to be referenced soon |
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conflict
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Multiple memory locations mapped to the same cache locatio
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block (line)
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the minimum unit of information that is
present (or not) in a cach |
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early restart
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processor resumes execution as soon as the
requested word of the block is returne |
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requested word first
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requested word is transferred from the
memory to the cache (and processor) firs |
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direct mapped cache
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a memory block maps to
exactly one cache block |