Cse 675 Midterm

Front 1

Response time / Execution Time

Back 1

A user measurement - The time between the start and completion of a task including dis accesses, memory accesses, IO activities, operating system overhead, CPU execution time and so on

Front 2

Throughput/bandwidth

Back 2

Number of tasks completed per unit of time

Front 3

CPU Execution time / CPU time

Back 3

The actual time the CPU spends computing for a specific task

Front 4

user CPU time

Back 4

The CPU time spent in a program itself

Front 5

system CPU time

Back 5

The CPU time spent in the operating system performing tasks on behalf of the program

Front 6

Clock Cycle / Cycle/ Tick/ Period

Back 6

The time for one clock period, usually of the processor clock, which runs at a constant rate

Front 7

Clock period

Back 7

The length of each clock cycle

Front 8

Clock rate

Back 8

Inverse of the clock period. GHz

Front 9

CPU Exeuction time for a program (Equation)

Back 9

= CPU clock cycles for a program / Clock rate

Front 10

CPU Clock cycles (equation)

Back 10

= instructions for a program X average clock cycles per instruction

Front 11

CLock cycles per instruction (CPI)

Back 11

average number of clock cycles per instruction for a program or program fragment

Front 12

Instruction count

Back 12

The number of instructions executed by the program

Front 13

CPU Time (equation) (2)

Back 13

= (Instruction Count X CPI) / Clock Rate

OR

= Instruction Count X CPI X Clock cycle time

Front 14

Time (Equation)

Back 14

= (Instructions / Program) X (Clock cycles / Instruction) X (Seconds / Clock Cycle)

Front 15

Desktop Computer

Back 15

A general purpose computer owned by an individual or a small
group. Often used for word processing, video games, etc

Front 16

Server

Back 16

A general purpose computer that is accessed by many people via
a computer network. Large companies may use servers to
support e-commerce websites or enterprise-wide services. Small
companies may use servers for simpler tasks

Front 17

Supercomputers

Back 17

Servers used to support high-end scientific and engineering
applications, e.g., molecular-scale simulation

Front 18

Embedded computers (processors

Back 18

A computer inside another device used for running one
predetermined application

Front 19

Five classic components of a computer

Back 19

input, output,
memory, datapath, and control

Front 20

datapath + control = ?

Back 20

processor

Front 21

Moore's law

Back 21

The number of transistors on a single chip will double every two years

Front 22

What has happened with

1.) Processor Performance
2.) Power Density
3.) Clock rates

Back 22

1.) Increased
2.) Increased
3.) Hit a wall and started to decrease (why?)

-Too much power consumption/heat

Front 23

What is the only option for sustained performance growth?

Back 23

More cores on chip

Front 24

ALU

Back 24

Arithmetic Logic Unit

Front 25

Register File

Back 25

Where the ALU reads its input from and writes its output to

Front 26

Pipelining

Back 26

Technique to efficiently organize instructions sent to the ALU

Front 27

As we move to many cores how do we get instructions and data to the processor? (2)

Back 27

Big wire that goes to each core, multiple wires for each core

Front 28

Memory Structure

Back 28

The physical places were data and
instructions are stored. Can be organized in many ways.
The most common organization is hierarchical

Front 29

Memory Hardware

Back 29

Different properties of the hardware that affect the use and structure

Front 30

Resource consumption

Back 30

the number of units of a resource
used to complete task

(clock cycles)

Front 31

What are the only two ways to increase performance

Back 31

1.) Reduce length of the clock cycle
2.) reduce the number of clock cycles needed to run the program

Front 32

Benchmarks

Back 32

Set of programs that measure performance

Front 33

Micro-Benchmarks

Back 33

Test a particular component of a system

Front 34

Macro-Benchmarks

Back 34

Test the whole system on real world simulations of data

Front 35

Principles of Machine Design (2)

Back 35

1.) Instructions are represented as numbers and are indistinguishable from data

2.) Programs are stored in alterable memory just like data

Front 36

Cisc

Back 36

Complex Instruction Set Architecture

Front 37

Risc

Back 37

Reduced Instruction Set Architecture

Front 38

Risc Vs Cisc

Back 38

Cisc Has instructions that take multiple clock cycles while in Risc each instruction only takes 1 clock cycle so pipelining is possible.

Cisc requires less memory to store instructions than risc

Cisc has emphasis on hardware while risc has emphasis on software

Front 39

What are the three instruction types in MIPS

Back 39

R, I, J

Front 40

Risc Design Principles (4)

Back 40

1.) Simplicity Favors regularity
2.) Smaller is faster
3.) Make the common case fast
4.) Good demand requires good compromise

Front 41

Alignment Restriction

Back 41

the memory address of a word must be
on natural word boundaries

Front 42

Big Endian

Back 42

Lowest address is the most significant

Front 43

Little Endian

Back 43

Lowest address is the least significant

Front 44

What does a logical shift mean

Back 44

fill with zeros

Front 45

data race

Back 45

Two memory accesses from different threads to the same
location, and at least one is a writ

Front 46

Atomic Exchange

Back 46

interchanges a value
in a register for a value in memory atomically, i.e., as one
operation

Front 47

activation record

Back 47

The segment of the stack
containing a procedure’s
saved registers and local
variables

Front 48

heap

Back 48

Dynamic data segment
(aka heap) for structures
that grow and shrink

Front 49

Combinational logig

Back 49

Output depends on current value of inputs

Front 50

Sequential function

Back 50

output depnds on current input and some internal states

Front 51

SR latch truth table

Back 51

S R Action
0 0 No Change
0 1 Q = 0
1 0 Q = 1
1 1 Restricted

Front 52

Order of how memory was designed

Back 52

SR latch, D Latch, D Flip Flop

Front 53

D flip flop truth table

Back 53

Clock D Q Qprev
Rising 0 0 X
Rising 1 1 X
Non-Ri X Qprev

Front 54

set-up time

Back 54

is the minimum time the D signal must be stable before the C signal falling edge

Front 55

hold time

Back 55

is the minimum time the D signal must be stable after C signal falling edge.

Front 56

Three state d-latch

Back 56

Adds enable signal that determines when the latch is for writing or reading

Front 57

SRAM

Back 57

static ram

large memory built on flip flops.

Piece together decoders instead of one large one.

Memory lost when power lost

Front 58

DRAM

Back 58

Value stored in capacitors but capacitors can leak. and as transistors and capacitors get smaller, leaking rate stays the same.

Front 59

Flash Memory

Back 59

Floating gate and control gate, word selector and bit line. Read bit line.

Writing a 0 requires Hot electron injection

Writing a 1 requires Quantum tunneling

Front 60

Flash Memory advantages/disadvantages

Back 60

Advantages:

Lasts a long time and no power consumption when idle

disadvantages:
not byte addressable

eventually can't write anymore because of tunneling

Front 61

PCRam

Back 61

Phase Change RAM

Uses chalconide glass that is heated or cooled and has different states

Benefits:
● Very fast reads and writes, though writes take
longer
● Under stable temperatures, memory storage is
permanent
● Write to individual words
● Highly scalable
● Negatives:
● Write limited (10^9 vs 10^5 for flash)
● Sensitive to temperature fluctuation

Front 62

What functions will our ALU perform (6)

Back 62

Add
Sub
SLT
Nor
Or
And

Front 63

Ripple Adder

And Carry Look Ahead

Back 63

Ripple is sequential, carry out from one goes to carry in of another


Look ahead calculates carrys for all

Front 64

How do we implement twos complement subtractor

Back 64

Make carry in 1 for first adder and flip all the b bits. Binvert line

Front 65

when does twos complement overflow happen

Back 65

1.) Sum of two positives is negative
2.) Sum of two negatives is positve

Front 66

How does mips handle overflow

Back 66

interrupt

Front 67

What comprises around 40% of computing time and can be only done _______

Back 67

Data management / serially

Front 68

What does Amdahls law state

Back 68

-Effort spent on parallel processing is useless instead of also increasing serial processing power

-‘law’ dictates how the maximum speedup
of a program depends on the amount of that
program requiring serial execution.

Front 69

What is Amdahls Law (equation)

Back 69

1 / (S + P/N)

Where S is non parallelizable part

P is parallizable part

N is number of processors

Front 70

What is the problem with parallel processing on many cores according to Amdahls law

Back 70

Always levels out the amount of speedup we can get

Front 71

Problems with Amdahls Law

Back 71

1.) Assumes P and N are independent

2.) the problem size increases with the
number of processors and the run time stays
constant!

Front 72

Generally what does Guastak;ljsad's law say

Back 72

Problems with Amdahls law have been overcome