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115 Cards in this Set
- Front
- Back
DFX |
Design For Excellence |
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DFX1 |
Design for Producibility and Reliability |
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It involves all the disciplines needed to manufacture and maintain an electronic product |
DFX |
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IPC 2581 |
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Heart of the electronics industry product realization |
Design |
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It is where the reality of that product vision begins to takes shape |
Design Phase |
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4 Design Requirements |
Performance Cost Reliability DFX |
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DFM |
Design for Manufacturing |
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DFA |
Design for Assembly |
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DFT |
Design for Test |
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DFR |
Design for Reliability |
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DFE |
Design for the Environment |
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3 IPC Structures |
Performance Classes Producibility Levels Board Types |
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Class where major requirement is funcrionality |
Class 1 |
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Environment may necessitate different: |
Materials Tolerance Final Product Configuration |
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Established to help communicate the design complexity of wthe manufacturers |
Producibility Levels |
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A printed board can have _________________ for different dedign features |
Different producibility levels |
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Types of Rigid Boards |
1 Single-Sided PCB 2 Double-Sided PCB 3 Multilayer Board without Blind or Buried Vias 4 Multilayer Board with Blind or Buried Vias 5 Multilayer Metal-Core Board without Blind Buried Vias 6 Multilayer Metal-Core Board with Blind Buried vias |
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They are important for proper circuit functioning and to assure all the physical requirements of the assembly are met |
Component Locations |
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An efficient placement facilitates a ________________________ and assures the design will meet |
quality routing of signal conductors |
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Acts as the hub of board design |
PCB Designer |
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Lialison between all groups, balancing demands so all requirements are met |
Printed Voard Designer |
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Components are usually placed in |
Rows and Colums |
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Space between the components placement |
Routing Channels |
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Support efficient fanout via |
Rows and columns of components with adequate space between |
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Allows connections from surface lands to internal circuitry on a predictable and testable grid |
Fanout vias |
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Permits the designer to move components to different locations to improve interconnection pathways, plan the shortest connection paths, show component lands that have not been connected and signal flow. |
Rat's Nest View |
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Required for unused logic pins |
Pull-up or pull-down resistors |
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Composed of components that can provide state information 1 or 0 as a function of the overall circuit |
Digital Circuits |
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Characterized by high pin count components that produce many signals |
Digital Designs |
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Routing of return circuitry is considered first and the signal routing second |
Digital Designs |
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Usually made up of discrete devices, and provide the waveform characteristics necessary to describe a circuit |
Analog Circuits |
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Characterized by low-pin count compinents with just a few signals per components |
Analog Designs |
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Component locations must be compatible with any defined |
Height restrictions |
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Flow of electricity ina an electronic system |
Current |
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Maximum Current that can be carried continuously by a conductor without degradation of the product |
Current Carrying Capacity |
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Property of conductors that resist the flow of electrons |
Resistance |
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Has a very low resistance to current flow |
Copper |
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Ideal conductive materials |
Low resistance to electricity |
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Useful in determining heat rise of conductors that are required to carry heavy currents |
Ohm's Law |
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By-product of power or work |
Heat |
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Conversion of energy from one form to another |
Power |
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Formula of power |
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When current flows through a wire or trace, it generates |
Electeic field and magnetic field |
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Magnetic field lines around a long wire which carries an electeic current form_____ |
Concentric circles around the wire |
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Unwanted radiated electro-magnetic energy that couples into electrical conductors |
EMI |
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The use of ____________ can also reduce electeo-magnetic interference upon devices, circuits or portions of circuits |
Return or voltage planes as shields |
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Act as shields to prevent crosstalk between traces in the z-axis |
Plane Layers |
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External plane layers can |
Protect from stray EMI Minimize EMI Emissions |
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Copper Clad Laminated are made up of |
Resin System Reinforcement Copper foil |
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Sheets of reinforcement coated with resin |
Prepreg or B stage |
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Fully cured material |
Core |
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Partially cured material |
Pre-preg |
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Most popular reinforcement |
Woven Glass |
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Provides structural strength and can be organic or inorganic |
Reinforcement |
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Most popular resin system |
Epoxy |
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Natural or synthetic resinous material |
Resin System |
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Lead Free soldering means |
Higher Temperature diring processing |
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Drives the need for higher temperature laminate |
Lead free soldering |
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Added to epoxy resin in order to make it more stable |
Additional properties as fillers |
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Dielectric or insulated metal sheet |
Base material |
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Base material can be |
Rigid Flexible Rigid Flex |
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Most common thickness of laminate cores of rigid base for multi layers |
4, 8, 5, 10 |
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Minimum thickness of rigid base material for multi-layer boards |
2 mils |
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Most common type of copper on rigid printed boards |
Electrodeposited ED |
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Wrought |
Rolled Annealed |
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Used for flex circuits because of its superior ductility |
Rolled Annealed |
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Shape of etched traces are |
Trapezoidal |
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Copper lost during etch |
1/2 mil per side per ounce if copper |
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The mechanical mechanism that holds the copper to the base material |
Resin |
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Happens when there's insufficient resin to provide dielectric integrity and stress relief |
Glass Crush |
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More expensove than foil construction |
Core construction |
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Construction often used for boards needing to meet tightly controlled impedance requirements |
Core construction |
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Construction for most rigid boards and preferred by vendors |
Foil construction |
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It is common practice for fabricators to compensate the original electronic data when they create their production floor film to account for their process variations |
FYI 😊 |
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Core material __________ during etch processes depending on how much total copper is removed |
Shrinks |
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It forces the fabricator to make major adjustments to your film |
Unbalanced copper distribution on layers |
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The board stackup should mirror around _________ in the z axis to prevent ____________ |
Centerline, warpage |
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Manifests as Bow and Twist |
Warpage |
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Undesirable deviations from a printed board's flatness |
Bow and twist |
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All four corners are in same plane |
Bow |
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Only three corners are in same plane |
Twist |
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Maximum vertical displacement for bow and twist diagonal length for SMT |
0.75% |
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Maximum vertical displacement for bow and twist diagonal length for SMT |
1.5% |
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Interfacial connections |
Plated Thru Holes |
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Plated holes are drilled ________ larger than the finished hole size for plating requirements |
2 to 4 mils |
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Processes that prepare the hole wall for electroless copper deposition |
Desmear and Etchback |
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Removes only resin smeared over the exposed ends of conductors due to drill heat |
Desmear |
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Remive sopper burrs after drilling |
Deburring |
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Controlled removal of nonmetallic materials from the hole walls |
Etchback |
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Removes resin smear, exposes internal condyctor surfaces for plating |
Etchback |
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Used on pcb for component thru holes and vias fully circumscribe the hole |
Lands |
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Minimun desired amount of copper material left around the hole after processing |
Annular ring requirement |
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Considers production tooling tolerances and process variations in order to meet the requirements of a fabricated board |
Fabrication Allowance |
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Drill sizes come in increments of |
2 mils |
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Three different methodology for hole locations |
Bilateral Tolerance Zone Positional Tolerance Zone Bonus Tolerance Zone |
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Holes are at the smallest Pins are at maximum |
MMC |
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Holes at maximum size Pins at smallest size |
LMC |
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Holes in boards are produces using |
Mechanical drilling or laser drilling |
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Holes mostly with CEM |
Punching |
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If a desired drill size falls between readily available standard drill bit size |
Round up to a larger size |
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# of drill size per board as sweet spot |
10 drill sizes |
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Bilateral tolerances for finished hole Level A |
0.0079" |
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Bilateral tolerances for finished hole Level B |
0.006 |
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Bilateral tolerances for finished hole Level C |
0.004 |
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Used as starting base for all rigid pcb |
Copper clad laminate |
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Metal clad material with copper as the conductive material |
Copper clad laminate |
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Etch Factor |
V/X |
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Occurs when the plating thickness exceeds the resist thickness |
Outgrowth |
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Also used as a method to remove heat from the components |
Copper |
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To accomodate variations in registration of the different conductive layers or hole locations |
Manufacturing allowance |
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A land on a specific layer that has no connection on that layer |
Non functional pad |
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For layers greater than ________, it is recommended to remove non functional pad |
10 layers |
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Large conductive areas ______ or larger covered with _____ increases the blistering warping or heat shielding during wave or reflow |
118 mils, solder mask |
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Large areas more than ______ diameter may be broken up into a ______ |
1.00", crosshatched |