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13 Cards in this Set
- Front
- Back
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Asynchronous Counter
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Type of counter in which each flip-flop output serves as the clock input signal for the next flip-flop in the chain.
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Asynchronous Inputs
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Flip-flop inputs that can affect the operation of the flip-flop independent of the synchronous and clock inputs.
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Clocked J-K Flip-Flop
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Type of flip-flop in which inputs J and K are the synchronous inputs.
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D Latch
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Circuit that contains a NAND gate latch and two steering NAND gates.
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Edge-Sensitive
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Manner in which a flip-flop is activated by a signal transition. A flip-flop may be either a positive- or a negative-edge-triggered flip-flop.
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Level-Sensitive
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Enabled by a logic HIGH or LOW level.
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PRESET
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Asynchronous input used to set Q=1 immediately.
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RESET / CLEAR
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Asynchronous input used to set Q=0 immediately.
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Rising Edge
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The part of a pulse where the logic level is in transition from a LOW to a HIGH.
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Shift Register
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Digital circuit that accepts binary data from some input source and then shifts these data through a chain of flip-flops one bit at a time.
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State Machines
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A synchronous sequential circuit, consisting of a sequential logic section and a combinational logic section, whose outputs and internal flip-flops progress through a predictable sequence of states in responds to a clock and other input signals.
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Synchronous Counter
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Counter in which all of the flip-flops are clocked simultaneously.
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Trigger
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Input signal to a flip-flop or one-shot that causes the output to change states depending on the conditions of the control signals.
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