Ths Fry Digital Electronics Vocabulary 2.5

Front 1

Compiler

Back 1

The process used by CPLD design software to interpret design information (such as a schematic or text file) and create required programming information for a CPLD.

Front 2

Complex PLD (CPLD)

Back 2

A digital device consisting of several programmable sections with internal interconnections between the sections.

Front 3

Design Entry

Back 3

The process of using software tools to describe the design requirements of a PLD. Design entry can be done by entering a schematic or a text file that describes the required digital function.

Front 4

Field Programmable Gate Array (FPGA)

Back 4

Class of PLDs that contain an array of more complex logic cells that can be very flexibly interconnected to implement high-level logic circuits.

Front 5

Fitting

Back 5

Assigning internal PLD circuitry, and input and output pins, to a PLD design.

Front 6

JEDEC

Back 6

Joint Electron Device Engineering Council.

Front 7

JEDEC File

Back 7

An industry standard form of text file indicating which fuses are blown and which are intact in a programmable logic device.

Front 8

JTAG

Back 8

Joint Test Action Group. A standards body that developed the format for testing and programming devices while they are installed in a system.

Front 9

JTAG Port

Back 9

A four-wire interface specified by the Joint Test Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit.

Front 10

Programmable Logic Device (PLD)

Back 10

Digital integrated circuit that can be programmed by the user to implement any digital logic function.

Front 11

Programming

Back 11

Transferring design information from the computer running PLD design software to the actual PLD chip.

Front 12

Simple PLD (SPLD)

Back 12

A PLD with a few hundred logic gates and possibly a few programmable macrocells available.

Front 13

Target Device

Back 13

The specific PLD for which a digital design is intended.

Front 14

TCK

Back 14

Test Clock. The JTAG signal that drives the JTAG downloading process from one state to the next.

Front 15

TDI

Back 15

Test Data In. In a JTAG port, the serial input data to a device.

Front 16

TDO

Back 16

Test Data Out. In a JTAG port, the serial output data from a device.

Front 17

TMS

Back 17

Test Mode Select. The JTAG signal that controls the downloading of test or programming data.