Test 2 Vocabulary

Front 1

Motorola 68000

Back 1

this CISC microprocessor has 16 programmer-visible registers available and was used in the original Apple Macintosh

Front 2

NaN (Not a Number)

Back 2

this is the result of the operation 0.0/0.0 is performed on a system with IEEE-754 floating-point arithmetic

Front 3

Delayed branch

Back 3

a technique used in pipelined CPUs where the instruciton immediately following a control transfer instruction is executed as though it came before the control transfer

Front 4

One-operand instructions

Back 4

these would be a characteristic of an accumulator-based machine

Front 5

Vertical microprogramming

Back 5

technique used to reduce the size of microprogram memory by encoding bit fields to represent mutually exclusive control signals

Front 6

MIPS R4000

Back 6

this was one of the first superpipelined microprocessors using one 8-stage pipeline

Front 7

shift-add algorithm

Back 7

this is the description of Booth’s algorithm

Front 8

Program counter

Back 8

register to keep track of instruction execution

Front 9

Pipeline register

Back 9

this is used to separate one stage of the pipeline from the other

Front 10

Two-operand instructions

Back 10

instructions where two operands are needed; one source operand can double as a destination operand being overwritten by the result of the operation

Front 11

Carry lookahead adder (CLA)

Back 11

this type of addition circuit develops all carries in logic, directly from the inputs, rather than waiting for them to propagate from less significant bit positions

Front 12

Op code

Back 12

the portion of the machine code language instruction which specifies the operation to be done by the CPU

Front 13

Positive infinity

Back 13

this is the result when the operation +1.0/0.0 is performed on a system with IEEE-754 floating-point arithmetic

Front 14

RISC

Back 14

Reduced Instruction Set Computer; The idea was to make the hardware as fast and as simple as possible by eliminating microcode and explicity encouraging pipelining of the hardware. Any task that cannot be quickly and conveniently done in hardware is left for the compiler to implement by combining simpler functions

Front 15

DEC Alpha 21064

Back 15

this microprocessor family is both superscalar and superpipelined in its design

Front 16

Zero

Back 16

number in floating-point standard which cannot be normalized, and is not negative infinity

Front 17

Zero-operand instructions

Back 17

These would be characteristics of a stack based instruction set

Front 18

Booth’s algorithm

Back 18

this can be efficiently used to multiply signed integers

Front 19

Wallace tree

Back 19

a structure comprised of multiple levels of carry-save adders (CSAs)

Front 20

microPC

Back 20

this keeps track of the location of the next microword to be retrieved from microcode storage

Front 21

Delayed load

Back 21

a feature of some instruction sets that is used to cover up a potential performance penalty associated with the pipelined information

Front 22

Carry Save Adder

Back 22

a set of full adders, one per bit position; it is similar to a ripple-carry adder with the important exception that the carry-out of each adder is not connected to the carry-in of the next more significant adder

Front 23

Horizontal microprogramming

Back 23

a technique used in microprogrammed control unit design in which mutually-exclusive control signals are not encoded into bit fields, thus eliminating the need for microinstructions

Front 24

VLIW

Back 24

a type of computer architecture that relies heavily on the compiler technology to exploit instruction-level parallelism

Front 25

Overlapping Register Windows

Back 25

a technique used in SPARC architecture to speed up procedure calling by avoiding the use of stack frames to pass parameters

Front 26

Negative infinity

Back 26

this is the result of the operation -1.0/0.0 is performed on a system with IEEE-754 floating-point arithmetic

Front 27

Super-pipelined architecture

Back 27

this type of processor architecture maximizes temporal parallelism by using a very deep pipeline with very fast stages

Front 28

Load-Store Architecture

Back 28

a feature of some computer architectures where “operate” instructions don’t have memory operands; their operands are found in CPU registers

Front 29

EPIC

Back 29

the architecture technology used in Intel’s IA-64 (Itanium) chips

Front 30

superscalar architecture

Back 30

a type of architecture that uses multiple, pipelined instructions execution units with resolution of inter-instruction dependencies done at run-time by the machine’s control unit

Front 31

machine code

Back 31

definition is not found in the book

Front 32

denormalized number

Back 32

exception in the IEEE-754 standards for numbers that are nonzerio but is too small to be normalized (that is less than 1.0 time 2 to the smallest exponent)

Front 33

one

Back 33

number of a single quantity used to confuse people; between +-infinity, NaN, and 0

Front 34

non-restoring division

Back 34

not found in book; is NOT restoring dvision, which is the algorithm for dividing binary numbers shown in the book

Front 35

CISC

Back 35

Complex Instruction Set Computer; a design philosophy which states that machine language instructions should have high-level functionality

Front 36

MAL

Back 36

Minimum Average Latency; this is the smallest mean number of clock cycles between initiation of operations into a pipeline

Front 37

minimum latency

Back 37

the smallest constant interval at which new operations can be started

Front 38

Hardwired Control unit

Back 38

directly wired sequential and combinational logic for handling controls

Front 39

Advantages of Hardwired

Back 39

faster run time, smaller chip space

Front 40

Disadvantages of Hardwired

Back 40

more monetary cost, slower compilation, complex design

Front 41

Microcoded control unit

Back 41

each individual operation is treated as a task to be implemented using programmable steps

Front 42

Advantages of Microcoded

Back 42

cheaper to implement, faster compilation, more dynamic (coded), compatibility-lower cost

Front 43

Disadvantages of Microcoded

Back 43

slower runtime, larger chip space

Front 44

Advantages of Superscalar

Back 44

factors small transistors, easier to write compilers, easier for diff. hardware imp. to be software imp.

Front 45

Disadvantages of Superscalar

Back 45

complicates CPU hardware, may not exploit all of ILP

Front 46

Advantages of VLIW

Back 46

each very long instruction process multiple instructions at the same time, large shared register set, keeps hardware simpler and typically faster

Front 47

Disadvantages of VLIW

Back 47

makes compilers slower and harder to write, not compatible of x86

Front 48

Similarities of Superscalar & VLIW

Back 48

both are multi-pipelined and use spatial paralellism