Ocr Computing 3.3 - Architectures

Front 1

Name 5 computer architectures

Back 1

Von Neumann
Co-Processor
Parallel Processor
Pipelining
Array Processor

Front 2

Describe the Von Neumann Architecture

Back 2

Uses a single processor for program control
that follows the fetch – decode – execute
Execution is performed one instruction at a time in a linear sequence
A single memory is used to store program instructions and the data for use with the instructions

Front 3

Disadvantage of Von Neumann

Back 3

it is slow as there is only one processor

Front 4

State the 3 stages, in order of the machine cycle used in class Von Neumann

Back 4

Fetch - Decode - Execute

Front 5

Name 5 registers

Back 5

program counter
memory address register
memory data register
current instruction register
accumulator
index register

Front 6

Describe what the program counter does

Back 6

It holds the ADDRESS of the next instruction

Front 7

Describe at what points the program counter is updated

Back 7

After the address currently in the PC is transferred to the MAR, a new address is loaded into the PC.

When a jump instruction is executed the address in the JUMP instruction is loaded from the CIR into the PC.

Front 8

Describe the purpose of the MAR

Back 8

Hold the address of the instruction or data that is to be fetched from memory

Front 9

The MAR stores the address of the instruction of data is that is to be fetched from memory. Where can this address come from?

Back 9

The PC passes the address of the next instruction to fetch

During decoding. the CIR passes the address of the operand that is to be used with the current instruction

Front 10

Describe the purpose of the MDR

Back 10

Holds data that is being transferred to and from memory

It holds instructions before they reach the CIR

Front 11

Describe the purpose of the CIR

Back 11

Holds the current instruction that is to be decoded.
The opcode part will be looked up in the opcode table to understand what to do
The address of the operand will be sent to the MAR

Front 12

Describe the purpose of the Accumulator

Back 12

Temporary storage within the ALU
Holds data being processed during calculations
Deals with the inputs and outputs in the processor

Front 13

Describe the FETCH part of the Fetch - decode - execute cycle

Back 13

The PC holds the address of the next instruction to be carried out

When the next instruction is needed it’s address is copied from the PC and placed in the memory address register

The PC is incremented by the program loader so it points to the next instruction

The address is found in memory and the contents of the address are placed in the memory data register

The contents of the MDR are then copied to the CIR ready for the decode stage

Front 14

Describe what happens when an instruction is decoded.

Back 14

The instruction in the CIR is split into its individual parts - opcode (e.g add) and address

The address is placed in the MAR and the data goes in the MDR

The control unit ‘decodes’ the operation code so the processor knows what to do

Front 15

Describe how a jump instruction is executed

Back 15

The contents of the PC are updated by moving the address part of the instruction in the CIR into the PC.

Front 16

Describe what is meant by a co processor

Back 16

This is an additional processor used for a specific task such as mathematical processes.

e.g maths co processor

Front 17

Describe the benefits of using a co processor system

Back 17

They improve processing speed by executing concurrently (at the same time) with the main processor.

Front 18

Describe the term pipe lining

Back 18

A processor is dvided into 3 parts. So one part can be fetching an instruction, another part can be decoding a different instruction and the final part can be running another instruction. This speeds up processing

Front 19

Describe why would a pipe line might be reset?

Back 19

When a jump instruction is executed. As the next instruction queued up to be executed is no longer the next one to be executed (the next one is the one inside the jump instruction)

Front 20

Describe a parallell processor system

Back 20

Uses multiple processors, controlled by a complex OS
Each works on a different task within the same job at the same time
Which can greatly speed up processes e.g arithmetic ones

Front 21

State one benefit of using a parallell processor system

Back 21

Can deal with multiple inputs at the same time and process them all simultaneously eg weather stations.

Front 22

State one disadvantage of using a parallell processor system

Back 22

In order to get the full benefits of Parallel processing programs need to have been specifically written for them.

Front 23

Describe what is meant by an array processor system

Back 23

This involves one processor but MULTIPLE ALUs.

An array processor is able to do the same calculation on multiple data locations

SIMD - Same instruction Multiple Data
This speeds up processing.

Front 24

What does RISC and CISC stand for?

Back 24

Restricted/Reduced Instruction Set Computer

Complex Instruction Set Computer

Front 25

Describe RISC

Back 25

Limited number of simple instructions available

Number of bits required to store the whole instruction set is small.

Can perform more complex instructions by executing several cycles of simple instructions

Front 26

Describe CISC

Back 26

Uses complex instructions each of which may take many cycles

Many instructions are available

Many address modes available