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21 Cards in this Set
- Front
- Back
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Instruction register |
-Dedicated tempoaray store register that stores current instruction to be executed - this is the instruction pre load -written from program memory, decoded by instruction decoder and read by control unit - it enables some degree of pipelining |
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Advantage of an instruction register |
- by storing instruction to be executed in a register we can use output to control other parts of the cpu so instruction can be executed |
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What is branching and what instructions in the PIC 16F84 cause a branching effect |
- a branch is an instruction in a program which causes a change in execution sequence of instructions in the program. normally instructions are executed one after another - ANY BIT SKIP INSTRUCTIONS (DECFZ, INCFZ, BTFSS, BTFSC) |
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How is the instruction register affected by branching |
-As instructions are executed as they appear in the program, branching instructions cause change in execution sequence therefore corrupts the pipeline and breaks it. Therefore the instruction register must be re populated, incurring a latency of 1 clock cycle |
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Working register |
Used to store one of the operands to be inputted into the ALU, stores result of ALU calculations |
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Control unit |
Interprets coded instructions and sends appropriate read and write instructions to the registers connected to the system bus. controls operation of cpu |
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Program counter |
- holds address in program memeory of next instruction to be executed, is normally incremented after each clock cycle -if a branch is needed can be acessed via system bus and adress of next instruction can be loaded into program counter. the program counter is modified by jump instruction -allows implementation of loops subroutines and if then operations. |
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Function of TRISA |
-port direction selection register, corresponds to port A pins, data direction reg allows each pin to be set individually as i/o before data is read or written to port data register portA |
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PORTA |
Port data selection register, i/o register that stores current value of I.O lines so that data can be copied and moved to other registers. |
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General purpose registers |
can be used as general variable storage by the user |
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Status register |
used to store carry flag from arithmetic operations -stores zero flags for selection instructions -some instructions are condiitons on state of a flag in the register, so allows some instructions to be controlled (btfss,sc) -manages bank switching - constrols program sequence by conditional branching based on flag state. |
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Program counter - how is an instruction executed |
-program counter starts at 0X00 - instruction on line 1 is fetched and stored in IC, instruction is decoded and performed by control unit. any file registers are modified and the resulting output if any are seen at the ports such as switching an LED ON |
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States of a tri state port |
- High impedence -lowimpedence LOW - output false -low impedence HIGH - output true low impedence indicatases output to a bus, indicates port is in ourput mode higg impedene state is an open circuit and can be ignored, only 1 low impedence at a time. high impedence indicates input. |
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Function of a watchdog timer |
-watchdog timer can reset an mp if stuck in an infinite loop - can be used to wake mp from sleep mode - can count down from a value before program is reset -recovery from errors or infinite loops |
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What is stack overflow |
- stack level on pic is 8 levels deep - call stack pointer exceeds the bound of the stack -stack stores return address of subroutines, stack overflow happens where therer are too many nested calls and as a result the number of memory slots are not enough. |
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What is pipelining |
-where operations are stored during previous instruction cycle, so multiple instructions are overalpped in execution - instruction reg stores op code of current instruction and fetches next one from memory whilst current is being executed. |
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in pipelining what happens if the next instruction is jump |
- contents of instruction register are invalid and are ignored - will take another instruction cycle to fetch valid op code from program memory - and take another cycle to complete |
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Two types of computer architectures (for exam) |
-von neuman single memory, program instructions and data are stored together -single bus is used to fetch instructions and data - advantage of this is reduced complexity - suffers from von neuman bottleneck harvard - parallel instructio and data fetch multiple memories for instruction and data multiple buses for signals advntage opf this is that access to each memories bus can occour during the same clock cycle |
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Two types of instruction sets (for exam) |
cisc - complex instruction set computer) over 80 instruction sets powerful and specialised advntage of this is that many instructions are macro like and one instruction can be used in the place of many - making code simpler risc - reduced set fewer than 30 instructions advnatge of this is that processor design is simpler and can be smaller, also consumes less power. |
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equ meaning |
assembler directive used to assign a label to a literal value address or register |
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addressing modes |
direct - address is specified after the instruction such as clrf portb immediate - address is built into the instruction word - movlw relative - modifying the program counter contents- using goto/call indirect - using pointers to reference an address in program memory |
