Microprocessor Test #2

Front 1

Requesting device that requests use of the 68000's buses by activating the BR(bus request) input

Back 1

Bus Master

Front 2

DTACK (data transfer acknowledge) is used by external circuitry to perform this...
means that every single byte must be
acknowledged before the next can be transfered

Back 2

Asynchronous data transfers

Front 3

performed using E, VMA, and VPA

Back 3

Synchronous transfers

Front 4

Output only (e.g. A1-A23)

Back 4

Unidirectional signals

Front 5

A state that represents a half cycle of the CLK input to the processor

Back 5

Cycle state

Front 6

The smallest amount of time in which the processor can perform any function

Back 6

State time

Front 7

this group deals with the microprocessor power and clock inputs

Back 7

Vcc, GND, CLK

Front 8

this group of signals is used to output the encoded processor status. Valid only when the AS signal is active(AS is low)

Back 8

FCo,FC1,and FC2

Front 9

this group of signals is provided to give the 68000 the capability to control older 68000 peripherals

Back 9

E (clock), VMA (valid memory address), and VPA (valid peripheral address)

Front 10

Out of E, VMA, and VPA, which one is an input only? This input is used to inform the 68000 that it has addressed a 68000 peropheral and that the data transfer should be synchronized with theE clock

Back 10

VPA

Front 11

This is used to generate the proper timing signals for 68000 peripherals

Back 11

E clock

Front 12

Synchronization is indicated by this output which goes low when the processor synchronizes with the E clock

Back 12

VMA (valid memory address)

Front 13

this group is used for interrupt control. These three inputs are used by external circuitry to request the encoded priority level of the hardware interrupt. Level 7 has the highest priority

Back 13

IPLo, IPL1, IPL2

Front 14

this interrupt input is the most significant

Back 14

IPL2

Front 15

this group is used for bus arbitration control. These signals are used to place the 68000 in a wait state while use is made of the hardware connected to its buses

Back 15

BR (bus request), BG(bus grant), and BGACK (bus grant acknowledge)

Front 16

When the processor is in a total processor reset (HALT+RESET), which registers does it affect?

Back 16

Supervisor stack pointer(vector 0) and program counter (vector 1), Status register now indicates a lecvel 7 interrupt priority. The trace bit and the supervisor bit is set.

Front 17

this group of signals is used for system control. They are "panic buttons"

Back 17

BERR(bus error), Reset, and Halt

Front 18

The 68000 will rerun the bus cycle if the Halt line is asserted before or at the same time as the BERR signal. This happens when the data and address buses are put into what state?

Back 18

High impedance state

Front 19

Which state is "open"

Back 19

High impedance state

Front 20

What level indicates that there are no interrupts present?

Back 20

Level 0 (all three inputs are high)

Front 21

In what register is masking done for Interrupt level encoding?

Back 21

Status register

Front 22

Before the new bus master activates BGack. There are 4 conditions

Back 22

BG must be active
AS inactive
DTACK inactive
BGACK inactive

Front 23

this group contains five signals that are essential to the proper operatio of external hardware

Back 23

asynchronous bus control
AS,R/W,UDS,LDS, and DTACK

Front 24

This signal is used to indicate that a valid memory address exists

Back 24

AS (Address Strobe)

Front 25

This signal determines whether the current cycle is read or write

Back 25

R/W (Read/Write)

Front 26

These signals are used to get 8 bits of information to/from selected portions of the 68000 data bus

Back 26

UDS Upper data strobe) and LDS (lower data strobe)

Front 27

This controls data on bits 8 to 15 of the data bus (the even bytes)

Back 27

UDS

Front 28

This controls data on bits 0 to 7 (the odd bytes)

Back 28

LDS

Front 29

To transfer 8 bits of data either UDS or LDS needs to be active. To transfer 16 bits at once both UDS and LDS need to be what?

Back 29

Low

Front 30

A1-A23 are always used to transmit a memory address except during...

Back 30

Interrupt acknowledge cycle

Front 31

This bidirection bus is used to transfer data between the processor and the outside world

Back 31

D0-D15

Front 32

This gives the ability to drive many more devices than the processor's address/data lines do

Back 32

Buffer

Front 33

The signals involved with memory access

Back 33

D0-D15,A1-A23,AS,R/W,UDS,LDS,DTACK

Front 34

The signals involved with I/O to peripherals

Back 34

E, VMA, VPA, and all memory signals except DTACK

Front 35

The signals involved with interrupts

Back 35

IPL0, IPL1, IPL2, FC0-FC2, and A1-A23

Front 36

Bus arbitration signals are

Back 36

BR, BG, and BGACK