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112 Cards in this Set
- Front
- Back
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Exa (E)
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10^18 (speed/time), 2^60 (data storage)
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Peta (P)
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10^15 (speed/time), 2^50 (data storage)
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Tera (T)
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10^12 (speed/time), 2^40 (data storage)
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Giga (G)
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10^9 (speed/time), 2^30 (data storage)
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Mega (M)
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10^6 (speed/time), 2^20 (data storage)
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Kilo (K)
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10^3 (speed/time), 2^10 (data storage)
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milli (m)
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10^-3 (speed/time), 2^-10 (data storage)
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micro (μ)
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10^-6 (speed/time), 2^-20 (data storage)
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nano (n)
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10^-9(speed/time), 2^-30 (data storage)
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pico (p)
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10^-12 (speed/time), 2^-40 (data storage)
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femto (f)
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10^-15 (speed/time), 2^-50 (data storage)
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atto (a)
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10^-18 (speed/time), 2^-60 (data storage)
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unsigned integer byte
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8 bits long, 0-255
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unsigned integer word
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16 bits long, 0-65,535
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unsigned integer double word
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32 bits long, 0-2(^32)-1
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unsigned integer quad word
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64 bits long, 0-2(^64)-1
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signed integer byte
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8 bits long, -128-+127
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signed integer word
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16 bits long, -32,768-+32,767
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signed integer double word
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32 bits long, -2(^31)-2(^31)-1
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signed integer quad word
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64 bits long, -2(^63)-2(^63)-1
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overflow condition
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a number that cannot be expressed in the current bit string you are working with
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logical shift
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used to multiply and divide unsigned intergers
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Shift logical left (SHL)
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used to multiply unsigned integers by 2(^n), where n are the bits shifted
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Shift logical right (SHR)
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used to divide unsigned integers by 2(^n), where n are the bits shifted
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Arithmetic shift
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used to multiply and divide signed integers
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shift arithmetic left (SAL)
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used to multiply signed integers by 2(^n), where n are the bits shifted
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shift arithmetic right (SAR)
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used to divide unsigned integers by 2(^n), where n are the bits shifted
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Rotation
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used for encryption, like the Caesar cypher
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IEEE
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Institute of Electrical and Electronics Engineers
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IEEE-754
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floating-point standard, where numbers are broken into 3 parts: sign bit, exponent and significand
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ASCII
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American Standard Code for Information Interchange, 8-bit representation of Latin alphabet
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Unicode
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16 bit, all world's languages represented
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Analog signal
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continuous sigjnalswith potential for infinite resoluton
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common audio formats
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1. WAV-Waveform Audio Format
2. MP3- Moving Pictures Experts Group, v1, Audio Layer-3 |
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common image formats
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1. BMP - bitmap
2. PNG - portable network graphics |
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data compression
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a reduction in data size so that data can be stored or transmitted mloreefficiently
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lossless compression
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reduces size w/out losing quality
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lossy compression
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reduces the file size smaller than lossless, but sacrifices quality of the file to do so
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ZIP
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Windows file compression utility
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GZIP
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*nix-based file compression utility
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Storage-program concept
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modern architecture using a:
CPU-processor memory-storage area for programs when running I/O-input and output devices for interaction |
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Little Man Computer
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created by Dr. Stuart Madnick @ MITin 1965 and revised in 1979, which is still an accurate representation of how computers work
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software
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a sequence of instructions written to perform a specified computer task
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hardware
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tangible computer components
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assembly language
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low-lvl programming language for computers where each statement corresponds to a single machine language instruction
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machine language
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a system of instructions executed directly by the CPU in binary
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LMC Accumulator
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3 digit GPR used by the ALU. Executes arithmetic operations and logic decisions, temporarily holds input and output data
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LMC Program Counter (PC)
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2 digit SPR used to point the CU to the correct memory address of the next instruction
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Instruction Register (IR)
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3 digit SPR used by the decoder to decode the instruction
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Memory Address Registry (MAR)
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2 digit SPR used to point to the correct memory address to read/write data
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Memory Data Register (MDR)
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3 digit SPR used to hold data to be read/written to the A or memory
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mnemonics
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represents instructions for LMC to execute
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machine code
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opcodes after assembly to instruct the computer on the instructions and order to execute
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Code segment
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hold machine code
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Data segment
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holds data defined within the code
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Heap segment
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holds data of 2 types: initialized and uninitialized (run-time), houses linked list
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Stack segment
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holds temp data, like CALs and RETs, operates in LIFO
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Subroutine
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segment of code within a program that performs a specific task that is relatively independent of the rest of the program
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Big Endian
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read left to right, top down, used in ARM processors
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Little Endian
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read right to left, bottom up, used in x86 processors
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LMC Operand addressing
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Immediate - register load
Direct -memory data load Indirect (offset)- data-> mem addy -> same data-> mem addy Indexed/based (offset) - 2 are added for field locator |
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CISC
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x86, several low-lvl operations combinedinto one instruction
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x86 GPRs
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Accumulator - AX, (EAX - 32 bit, RAX-64 bit)
Base- BX, base pointer to data segment Counter - CX, counter for stringand loop ops Data- DX, used for I/O ops for data xfer Source - SI, string ops source pointer Destination - DI, string ops destination pointer Stack Pointer - SP, top of stack Base Pointer - BP, base of stack |
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x86 Segment Registers
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CS - points to the code
DS - points to the data SS - points to the stack ES - points to extra data in a tiered approach FS - follows ES GS - follows FS |
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x86 Program Status and Ctrl Register
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reports the status of the program being executed (FLAGS)
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Instruction Pointer Register (IP)
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contains a pointer to next instruction to be executed
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x86 data types
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Fundamental- base data type
Numeric- allows for math ops to be performed Floating Point- allows for fractions Pointer- allows reference to memory location Bit Field- contains bits for Boolean values String- multiple segments of bits or bytes Packed SIMD- single instruction, multiple data |
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x86 Instruction types
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Data transfer
Arithmetic Logical Bit Manipulation Ctrl Transfer String I/O MMX Flag Floating point Streaming SIMD Extension (SSE) |
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x86 operand addressing
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Immediate
Register Memory Segment Offset Assembler and Compiler I/O Port |
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x86 modes of operation
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Real-address
Protected - the default mode Sys Mgmt |
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RISC
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1 instruction for 1 operation, data processing in registers not in memory
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ARM
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Advanced RISC machine
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ARM GPRs
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13, 32-bit registers (R0-R12)
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ARM SPRs
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stack pointer (R13)
link register (R14) |
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Current Program Status Register
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CPSR holds status of last instruction, such as flags. SPSR saves a copy when switching modes
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ARM Instruction Pointer
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the PC or R15 holds current instruction address
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Arm Data Types
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Fundamental
Numeric Pointer Packed SIMD |
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ARM Instruction Types
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Data Transfer
Arithmetic and Logic Ctrl Transfer Flag SIMD |
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ARM operand addressing
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Immediate
Register Indirect Pre-indexed Post-indexed |
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ARM Modes of Operation
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User (usr)
System (sys) Supervisor (svc) Abort (abt) Undefined (und) Secure Moniter (mon) IRQ FIQ |
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ARM Privilege levels
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PL0 - user mode
PL1 - all others |
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Bus lines
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address line-location to read/write data
data line-transfers data ctrl line-interrupts and syncing, indicates who has access to the bus |
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bridge
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allows for communication of dissimilar buses since buses talk indifferent languages and speeds
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I/O Module
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interfaces with the processor, memory and 1 or more peripheral devices; similar to a CPU, but for only one purpose, may or may not have own memory
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Device Interface
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allows for a physical way for the peripheral devices to interface w/ computer
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Bus Topologies
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Multipoint-more than 2 components
point to point-2 components |
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Bus Protocols
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serial - sequential, asynchronous; relies on handshaking
parallel - sequential over multiple data lines, higher overhead |
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Handshaking
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series of steps to coordinate asynchronous communication in which each party agrees before moving to the next step
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buffering
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act of storing datain a region of memory known as a buffer
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Bus arbitration
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resolves bus ctrl conflicts
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daisy-chain arbitration
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bus access from highest to lowest priority
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centralized parallel arbitration
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direct ctrl lines for each device serviced by a master
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distributed using self-select arbitration
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highest priority between devices themselves
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distributed using collision detect arbitration
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device asks again, if collision is detected first time
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Programmed I/O
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periodically checks I/O devices for need to service
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Interrupt driven I/O
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asynchro; employs interrupts to CPU for I/O device service
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exception
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synchro; disrupts prgm execution
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maskable
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CPU can ignore these
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unmaskable
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CPU must service this
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fault
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incorrect memory access or division by zero at the A
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trap
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software invoked; the Windows "are you sure?" window
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abort
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serious error; hardware errors or illegal sys table value
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memory-mapped I/O
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memory address space assigned to I/O devices
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direct memory access
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provides a device ctrlr to/from memory w/out involving the processor
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cache
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small, fast memory on CPU chip
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replacement policy
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how blocks of data in the cache are replaced
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first in, first out
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oldest block becomes first victim; high thrashing
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least recently used
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least used block in cache is first used
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random
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solves thrashing; random selection of victim block
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direct mapped
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each memory addy mapped to one or more cache addresses
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fully associative
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allows any memory block to be stored in any cache block
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locality principle
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the blocks around the transferred block are moved as well
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