Issap - Domain 4 - Requirements Analysis And Security Standards, Guidelines And Criteria

Front 1

Temporary storage available to the computer, usually in the form of RAM.

Back 1

Real storage

Front 2

Non-volatile memory sources such as CDROMS, hard disks, and USB drives.

Back 2

Secondary storage

Front 3

Space on secondary storage used to increase the apparent primary storage.

Back 3

Virtual memory

Front 4

Storage that must be accessed in order from beginning to end.

Back 4

Sequential

Front 5

Volatile memory that can be static or dynamic.

Back 5

Random access memory (RAM)

Front 6

ROM devices that may be erased and rewritten through the use of an ultraviolet light.

Back 6

Erasable programmable read only memory (EPROM)

Front 7

ROM devices that may be erased and rewritten through the use of electricity.

Back 7

Electrically erasable programmable read only memory (EEPROM)

Front 8

Four operating states of the CPU.

Back 8

Ready, supervisory, problem, wait

Front 9

An executing program with its own memory space.

Back 9

Process

Front 10

Streams of execution.

Back 10

Threads

Front 11

Systems that can process multiple threads simultaneously.

Back 11

Multithreading

Front 12

Systems that can process multiple processes simultaneously.

Back 12

Multitasking

Front 13

Systems that can use more than one processor simultaneously.

Back 13

Multiprocessing

Front 14

The ring that the kernel operates in.

Back 14

Ring 0

Front 15

The ring that OS components other than the kernel operate in.

Back 15

Ring 1

Front 16

The ring that input/output software operates in.

Back 16

Ring 2

Front 17

The ring that user level applications operate in.

Back 17

Ring 3

Front 18

Security mode where each subject must have clearance for all information on the system and a need to know for all information.

Back 18

Dedicated

Front 19

Security mode where each subject must have clearance for all information on the system and a valid need to know some of the information.

Back 19

System high

Front 20

Security mode where each subject must have clearance for most restricted information on the system and a valid need to know.

Back 20

Compartmented

Front 21

Security mode where some subjects do not have clearance for all information and each subject has need to know for all the information that they will access.

Back 21

Multilevel

Front 22

The combination of protection mechanisms within a system.

Back 22

Trusted computing base (TCB)

Front 23

Methods used to protect resources assigned to one protection domain from processes in another protection domain.

Back 23

Data hiding or layering

Front 24

Four access control models.

Back 24

State machine, access matrix, take-grant, bell-lapadula

Front 25

Access control model that allows the operating system to transition only between a series of well defined states.

Back 25

State machine model

Front 26

Access control model that uses a combination of read, write, and execute permissions assigned to various users.

Back 26

Access matrix model

Front 27

Access control model that uses directed graphs to illustrate security permissions that one object can take from another and those that the object can grant to another object.

Back 27

Take-grant model

Front 28

Access control model that is a lattice model designed to strictly enforce the military's MAC model. No read up, no write down.

Back 28

Bell-lapadula

Front 29

Two integrity models.

Back 29

Biba, clark-wilson

Front 30

A lattice-based modelthat is similar to the Bell-lapadula model. No write up, no read down.

Back 30

Biba

Front 31

Integrity model that enforces separation of duties to maintain data integrity.

Back 31

Clark-wilson

Front 32

Rainbow series book that includes the DoD trusted computer systems evaluation criteria (TCSEC).

Back 32

Orange book

Front 33

Rainbow series book that included the trusted network interpretation of TCSEC.

Back 33

Red book

Front 34

Seven criteria for evaluating systems as specified in the TCSEC.

Back 34

Security policy, identification, labels, documentation, accountability, lifecycle assurance, continuous protection.

Front 35

Seven TCSEC designations.

Back 35

D, C1, C2, B1, B2, B3, A1

Front 36

TCSEC designation indicating minimal protection.

Back 36

D

Front 37

TCSEC designation indicating discretionary protection and requiring DAC, identification and authentication, assurance of system architecture and integrity, lifecycle assurance of security testing, and documentation.

Back 37

C1

Front 38

TCSEC designation indicating controlled access protection systems that must meet all of the C1 criteria plus object reuse policy and audit.

Back 38

C2

Front 39

TCSEC designation indicating labeled security protection systems that must meet all of the criteria for C2 plus, label integrity policy, policies on exportation of labeled information to single level devices, multilevel devices, and human readable output, MAC, and lifecycle assurance of design specification and verification.

Back 39

B1

Front 40

TCSEC designation indicating structured protection systems that must meet all of the criteria for B1 systems plus policies that address subject sensitivity labels and device labels, trusted path for identification and authentication, additions to operational assurance of covert channel analysis and trusted facility management, and the addition of configuration management to lifecycle assurance.

Back 40

B2

Front 41

TCSEC designation indicating security domains systems that must meet all of the criteria for B2 systems plus trusted recovery operation assurance and use of a trusted computing base small enough that it can be subjected to rigorous testing.

Back 41

B3

Front 42

TCSEC designation indicating verified design systems that must be developed using a formal design specification and verification techniques that follow a five step model.

Back 42

A1

Front 43

Profiles which specify security requirements for a product.

Back 43

Protection profiles

Front 44

Design claims made by vendors to provide a structured system for the evaluation of information technology products.

Back 44

Security targets

Front 45

EAL level for functionally tested

Back 45

EAL1

Front 46

EAL level for structurally tested.

Back 46

EAL2

Front 47

EAL level for methodically tested and checked.

Back 47

EAL3

Front 48

EAL level for methodically designed tested and reviewed.

Back 48

EAL4

Front 49

EAL level for semi-formally designed and tested.

Back 49

EAL5

Front 50

EAL level for semi-formally verified design and tested.

Back 50

EAL6

Front 51

EAL level for formally verified design and tested.

Back 51

EAL7

Front 52

A comprehensive evaluation of the technical and non-technical security features of an IT system to establish the extent that the design and implementation meet a set of specified security requirements.

Back 52

Certification

Front 53

A formal declaration that an IY system is approved to operate in a particular security mode using a prescribed set of safeguards at an acceptable level of risk.

Back 53

Accreditation

Front 54

Unintended communications paths that allow the surreptitious transfer of information outside of normal security controls and mechanisms.

Back 54

Covert channel

Front 55

Covert channels that relay information by modulating consumption of system resources.

Back 55

Timing channels

Front 56

Covert channels that relay information between processes by writing data to a storage system.

Back 56

Storage channels.

Front 57

Attacks that siphon off small bits of data to gain through aggregation.

Back 57

Salami attacks

Front 58

Attacks that exploit differences between the time a process verifies the access permissions of a security object and the time that the permissions are used.

Back 58

Time of check/time of use (TOC/TOU)

Front 59

Attacks that attempt to execute malicious code through the exploitation of buffers that do not have proper bounds checking.

Back 59

Buffer overflow

Front 60

A processor that can execute multiple instructions at the same time.

Back 60

Superscalar.

Front 61

A processor that can execute only one instruction at a time.

Back 61

Scalar