I/o

Front 1

What are I/O controllers?

Back 1

Also known as I/O adapters/modules provide the Cpu with a programming interface

Front 2

What are the types of I/O ports?

Back 2

Data ports and Control ports

Front 3

What do data ports do?

Back 3

They are used to pass data from/to Cpu to the I/O device

Front 4

What do Control ports do?

Back 4

They are used to issue commands and check device status(similar to Cpu rflags). Write to specific bits to issue commands or read specific bits to check device status.

Front 5

Explain the separate address space.

Back 5

1. I/O ports have separate address spaces.
2. The control bus signals if a transfer is the main memory or to I/O.
3. Intel 64 provides 64k 8-bit I/O ports from 0 to 65535. e.g. in ax, value (read) OR out 35, ax (write)

Front 6

Explain memory mapped I/O?

Back 6

1.I/O ports appear as normal memory locations
2.Normal assembly instructions can be used

Front 7

Name the four I/O schemes

Back 7

1. Programmed I/O
2. Interrupt driven I/O
3. DMA I/O
4. I/O processor

Front 8

Explain Programmed I/O

Back 8

Continually poll a devices control port until it is ready the initiate transfer

Front 9

Explain Interrupt-driven I/O

Back 9

Initiate transfer then do something else. Device will "interrupt" the Cpu when the transfer is complete. On detecting an interrupt, control is transferred to device’s interrupt-handling procedure (interrupt handler)

Front 10

Explain DMA I/O

Back 10

Initiate large data(block) transfer. Device will transfer block to/from memory and then interrupt Cpu after block is transferred.

Front 11

Explain the I/O processor

Back 11

Dedicate complex I/O processing task to a dedicated processor.

Front 12

Show an example of data transfer using programmed I/O

Back 12

1. foreach byte in Block do
2. loop Read Status Bit(s) of CONTROL Port if Status Bit(s) indicate ERROR then “Handle” Error
3. exit when Status Bit(s) indicate DEVICE is “READY” endloop
4. Copy byte from Block to DATA Port
5. Issue Write Request by writing to Command bits in CONTROL Port endfor

Front 13

What are to trade-offs of Programmed I/O?

Back 13

1. Simple to program
2. Can guarantee response times
3. Poor Cpu utilisation
4. Multiple devices are awkward to handle.

Front 14

Interrupt-driven I/O trade-offs

Back 14

1. Big step forward when compared with programmed I/O
2. Interrupt-processing time is relatively expensive – some overhead with saving and restoring CPU state etc.
3. Bad for high-speed, high-data volume devices that might lose data if they are not serviced quickly enough
4. Bad if many devices continually require attention

Front 15

Explain how DMA I/O block transfer works?

Back 15

1. CPU writes start address of block, number of bytes of block and direction of transfer to DMA’s I/O ports and issues start command
2. DMA controller transfers block of data between the device and main memory without direct CPU intervention
3. On completion, DMA controller interrupts CPU

What the transfer time for n-bytes using interrupt and DMA I/O?,

Interrupt = (Time for 1 interrupt + Memory access time)* n
DMA = Time for 1 interrupt + (Memory access time)*n

Front 16

How does a device interrupt the Cpu?

Back 16

The device sends an interrupt signal to the Cpu along with an interrupt vector number identifying the interrupt

Front 17

What is an interrupt vector number?

Back 17

It is a number used to index the interrupt descriptor table (IDT) with 256 entries

Front 18

Where is the start address of the IDT held?

Back 18

In the IDT base register(IDTR)

Front 19

What is the CS register?

Back 19

Is the code segment register, is used alongside the IP register cs:ip in order the increase the max range of memory which can be addressed

Front 20

What are the sequence of action which occurs when calling an interrupt handler?

Back 20

1. Complete currently executing instruction
2. Push RFLAGS register onto the stack
3. Clear the interrupt bit in the RFLAGS to prevent further interrupts
4. Push CS register and return address
5. Jump to interrupt handler using IDT
6. To return, the handler executes iret which restores the state and jumps to the return address on the stack.

Front 21

How do you re-enable/disable interrupts?

Back 21

Call the instruction sti, (bit 9) to enable, cli to disable.

Front 22

Write a print driver

Back 22

TODO

Front 23

What does "top half refer to"?

Back 23

The code of the device driver, the interrupt handler which services the interrupt and checks for errors and copies data to/from memory area it shares with bottom half.

Front 24

What does the "bottom half" refer to?

Back 24

The bottom half runs as a schedulable thread within the O/S and interacts with the device via I/O ports, the top half(via shared memory) and the user level process

Front 25

What are the types of interrupts?

Back 25

1. External I/O devices generated interrupts(asynchronous): I/O devices sends an interrupt vector number to CPU via buses(vector numbers 32 -255).
2. Cpu generated interrupts(synchronous): e.g. divide-by-zero exception (vector numbers 0-18)
3. Software-generated instructions(synchronous): interrupts generated by software e.g. int 80h

Front 26

How are software interrupts called?

Back 26

Using syscall instruction,. Commonly used for calling operating system functions (system calls) where the address of the function need not be known and the privilege level must be escalated in a controlled fashion. Also known as traps.