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295 Cards in this Set
- Front
- Back
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describe opcode 1xx
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add - 1=opcode xx=operand
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which opcodes are branch
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BRA 6xx
BRZ 7xx BRP 8xx |
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name all the instructions and which position they're in
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ADD 1
SUB 2 STA/STO 3 LDA 5 BRA 6 BRZ 7 BRP 8 INP 901 OUT 902 "ass load of bras in brazil, brp, in out" |
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prom
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programmable ROM
volatile |
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eprom
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non volitile; specific UV light to erase
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eeprom
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non volatile; electric erasable
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PC to MAR
MDR to IR IR to MAR A- MDR -> A PC +1 to PC |
subtract
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pc to mar
mdr to ir inbox to a pc +1 to pc |
IN
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pc to mar
mdr to ir a to outbox pc +1 to pc |
out
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pc to mar
mdr to ir |
halt
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pc to mar
mdr to ir ir to pc |
branch
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pc to mar
mdr to ir if a=0:ir to pc else: pc1 to pc |
branch zero
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pc to mar
mdr to ir if a ≥ 0: ir to pc else: pc1 to pc |
branch pos
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pc to mar
mdr to ir ir to mar A+ mdr to A pc +1 to pc |
add/fetch execute
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2 types of busses
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single point and multi point
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risc means...
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reduced instr set processor
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risc computers have a __ bit word, and is ___ bytes
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32 bit
4 bytes |
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cisc means
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complex instruction set computer
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cisc computers have ___ data words
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variable length
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cisc computers ___ byte instructions
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16 byte
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stacks are ordered this way
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LIFO
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PC to mar
MDR to IR pc1 to pc ir [addr] to pc |
Call stack (push)
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pc to mar
mdr to IR stack to pc |
return (pop)
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which type of computer has 8 gen purpose registers
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cisc
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which type of computer has 32 gen purpose registers
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risc
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which computer has 64 gen purpose registers
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VLIW
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type of computer has 3 48 bit/128bit instruction
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EPIC
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type of computer has few address nodes
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RISC
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type of computer has 128 bit molequl and 4 32 bit atoms
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VLIW
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type of computer that has a code morphing layer
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VLIW
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Carusoe CPU
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VLIW
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parallel instruction x4
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VLIW
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type of computer, 5 bits to ID type of instruction
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EPIC
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itanium based cpu
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EPIC
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IRQ 8
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system cmos/realtime clock
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"here i am" address included in interrupt
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vector data word
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polls each device after interupt sig
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polled interupt
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unstoppable interupt
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non-maskable interupt
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cpu releases control of the bus
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DMA
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what does the cpu need to know when releasing for DMA
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how big, where:
location of data on device starting location size of block (512 byte blocks) direction (read or write) |
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order storage in speed/storage size
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registers
cache (sram) ram (dram) flash mag disk opt disk mag tape |
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name storage on a HD
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sectors
tracks blocks (smallest, 512bytes) Cylinders |
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2 types of velocity on a HD
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constant angular velocity
(bits on each track are the same) (same speed every track) Constant linear velocity |
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time a HD takes to transfer tracks
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seek time
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time it takes a HD to rotate to the beginning of a sector
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latency
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time it takes a HD to read data
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transfer time
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describe the anatomy of a HD block
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gap|header | data |gap
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how many cycles to read a HD in non-interleaving
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8 cycles
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spaced out blocks on a HD spacing time for error checks is called ___
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interleaving
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interleaving reduced the amount of rotations on a HD from ___ to ___
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8 to 3
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Raid 0
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striping
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raid 1
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mirroring
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raid 3
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striping with dedicated parity
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raid 5
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striping and distributed parity
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LMC has ___ mailboxes
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100
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when the source and destination are part of the command
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explicit addressing
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when the source or destination is not specified as an arguement but are part of the opcodes
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implicit addressing
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instructions reserved for the OS
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priviliged
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instructions that can be used by any program
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non-privilaged
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shift and rotate bits
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to multiply or divide by 2
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type of computer that has comparatively few general purpose registers
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CISC
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large number of varying addressing techs, specialized instructions, instruction words of varying sizes
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cisc
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many gen. purpose registers
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RISC
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only a few basic load and store instructions, most instructions operate only with registers
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RISC
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3 types of memory enhancements
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wide path memory access
memory interleaving cache (write thru/write back) |
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cpu changes a memory location, main memory is changed at the same time
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write thru cache
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main memory is not changed until cache is no longer needed, then copied back to main memory... faster
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write back cache
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a pair of registers in the cpu are connected via bus to the I/O module
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programmed I/O
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how many IRQ's are there
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32 (0-31)
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amount of time between timer interupts
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quantum
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2 types of abmormal event signal
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power interupt
divide by zero |
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3 conditions for DMA
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1 memory and the I/O must be connected
2 I/O module must be capable of accessing memory 3 way to control access to bus and memory so one thing is in memory at a time |
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IBM mainframe uses ____ to manage I/O to CPU/Memory
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Channels
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pie shaped selection on a HD
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sector
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like a floppy, 3000 rpm
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bernoulli
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explain why write back cache is better
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faster of the 2
one time write back to memory (vulnerable to power loss) |
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explain why write thru is worse
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must update L1, L2, main memory
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used to move data across busses
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programmed I/O
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which bus was developed as a topology by apple
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firewire
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multiple paths via independent cpu, to main cpu
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mainframe channeling
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what is the NIC in an ibm mainframe
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NIU (net interface Unit)
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what are i/o modules
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buffers, controls disks, registers and controls DMA, interupts cpu, copies from buffer to disks
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storage heiarchy
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fastest to increasing storage:
registers cache (SRAM) ram (DRAM) flash magnetic disc optical magnetic tape |
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cash ram
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SRAM
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ram type
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dram
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HD block size
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512
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what is constant angular velocity
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bits on each track are the same
same speed on every track |
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name the parts of a processor
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accumulator, memory, registers
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instruction size decreases memory size t/f
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false
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this increases efficiency
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stack
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port 79
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finger
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port 23
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telnet
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port 80
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http
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ftp data port
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20
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ftp control port
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21
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port 110
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pop
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port 25
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smtp
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2 types of magnetic tape
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sequential and linear
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type of mag tape where head rotates
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helical
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media with 650 mb storage (typical)
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optical
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optical block size
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2352
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whats a 1 and 0 represented by in an optical drive
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land and pit
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whats a land represent on an optical drive
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flat = 1
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whats a pit represent on an optical drive
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scatter = 0
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what uses exotic crystaline metal alloys
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magneto optical
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magneto optical has what difficiency
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slow seek
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ascii has _ and _ bit words
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7/8
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ascii hex that would indicate a windows machine
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0A 0D
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ascii hex that would indicate a unix machine
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0A
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ascii that starts the alphabet
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41 (capital letters)
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ascii alphabet
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41 + 26 = caps alphabet
61 starts lower case |
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ascii numbers
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30 - 39 = 1-9
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ascii blank space
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FF
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ascii periods
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2E
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encoding on mainframes
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epcidic
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whats epcidic stand for
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extended binary code decimal interchange code
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whats ascii stand for
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american standard code for information interchange
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whats BCD
|
binary coded decimal
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write out 253 in BCD
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0010 0101 0011
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name the 5 ways to increase system performance
|
1 multiple cpu
2 clock speed 3 wide instruction/data path 4 disk access 5 increase memory |
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whats tight coupled multiprocessing
|
multiple cpus share common resources like memory and I/O.
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what is loosely coupled multiprocessing
|
each cpu has memory and I/O devices (clusters)
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what is master slave multiprocessing
|
one cpu is reserved for the OS
that cpu controls scheduling/resources for the other cpus |
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what is symetrical multiprocessing
|
form of tightly coupled where OS can be executed by any cpu, each cpu is responsible for its own dispatching and resources are shared by all cpus
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what form of multiprocessing does intel use
|
master slave
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what form of multiprocessing does amd use
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SMP
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what type of topology uses point to point
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ring
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what is a cluster
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group of loosely coupled computers working together as a unit
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what are the 2 types of clusters
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shared disk
shared nothing |
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|
ethernet is also known as
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csma/cd
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name the top 4 gen purpose registers
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AX accumulator
BX base CX counter DX data |
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what is AX register
|
temp storage, arith ops
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what is BX register
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temp storage, arith ops, base address pointer
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in what register is the base address pointer
|
BX
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what is the CX register
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temp storage, arith ops, counter, index of array loops
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what is the DX register
|
temp storage, combines with AX for multiplication/division & other arith ops
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what are the bottom 4 gen registers
|
BP base pointer
SP stack pointer SI source index DI destination index |
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what is the BP register
|
base pointer for the current stack
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what is the SP register
|
pointer to current stack
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what is the SI register
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source index in array
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what is the DI register
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destination index in array
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what are the 7 addressing modes
|
register, immediate, direct, register deffered addressing, base addressing, indexed addressing, base indexed addressing
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x86 instructions are _ to __ bytes
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1 to 15
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what is the only required field in the x86 instruction
|
opcode
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most x86 opcodes are _ byte long
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1
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what are the common flag instructions
|
carry, parity, auxillary carry, zero, sign, trap, interrupt enable, direction, overflow
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what is the carry flag instruction
|
used by add/sub ops
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what is the parity flag
|
set when result of op contains even number of bits
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what is the aux carry flag
|
indicates carry or borrows during BCD arith
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what is the zero flag
|
set if result of op is zero
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what is the sign flag
|
set if the result is negative
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what is the trap flag
|
used in debugging to halt cpu after each instruction
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what is the interrupt enable flag
|
enable or disable hardware interrupts
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what is the direction flag
|
define the direction of memory for string ops
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what is the overflow flag
|
set if result of op is too big or small to fit in destination operand
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floating point instructions were added to the processor starting with the ______ processor
|
80486DX
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_____ and _____ instructions allow aperations like comparison and arithmatic on up to 8 numbers at a time
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mmx and simd
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the ____ address mode shows the source or destination is a register
|
register
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the ___ address mode = the data source is part of the instructions
|
immediate
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in ____ addressing the address of the source or destination is part of the instruction
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direct
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in _____ _____ _____ the address of the source or destination is found in a register
|
register deferred addressing
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in ____ addressing the source or destination is found by adding the value in the displacement field of the instruction to a base address stored in a register
|
base addressing
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in _____ addressing the address of the source or destination is calculated by adding a displacement specified in the instruction to the value in an index register
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indexed
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in ____ _____ addressing the address of the source or destination is calculated by adding both the value in the base reg and the index reg to the displacement in the instruction
|
base indexed
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the ____ address points to somewhere within the memory allocated for the program
|
logical
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the _____ address points to the map of the block of main memory
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physical
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___ mode uses 4 segment registers to point to blocks of memory allocated to a program
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real
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what is the real mode segment CS
|
code segment
|
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what is the real mode segment DS
|
data segment
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what is the real mode segment SS
|
stack segment
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|
what real mode segments were added in the 80386 processor
|
FS GS
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|
the ___ and ____ combine to point to the real mode address
|
segment register and logical address
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|
what is added to the data segment register, combined with the logical address to find the 20 bit address
|
0 at the LSB
|
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|
what is protected mode
|
instead of the segment register pointing to a block of memory, its reffered to as a selector register and points to an entry in a descriptor table for the base segment address
|
|
|
what did protected mode do?
|
allowed for multitasking, virtual storage, memory management which isolates OS and running tasks, and provided for efficient task switching
|
|
|
the isolation of the OS from running tasks was provided by _____
|
adding protection levels to the instruction sets
|
|
|
the OS runs at PL___
|
0
|
|
|
apps run at PL_
|
3
|
|
|
IA-64 itanium provides ___ 65 bit GP registers and ___ 80 bit floating point registers
|
128
|
|
|
which architecture has more gp regs?
|
power pc
|
|
|
what are the 7 categories for instructions in the powerpc
|
1 load/save
2 integer 3 floating point 4 flow control 5 processor control 6 memory control 7 vector |
|
|
powerPC cpu can be ___bit or ___ bit in size
|
32 or 64
|
|
|
the 32 bit powerPC has 32 bit gen and 32 bit address regs and can have up to __ bit virtual addressing
|
54
|
|
|
the 64 bit powerPC has 64 bit gp regs and address regs, and can address ___ bytes of memory
|
16 exabytes
|
|
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the load/store instructions in a powerPC contain instructions for loading ___, ____, and ____ and ____.
|
bytes, halfwords, words, and floating point words and double words
|
|
|
the powerPC 64 bit implementation can load/store stings, multiple words of data in groups up to __ at a time
|
32
|
|
|
this instruction in the powerPC does the normal arith functions, and can execute ___ and ___ instruction.
|
integer, rotate and shift
|
|
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this powerPC instruction set includes branch instructions for both ____ and ____ addressing instructions
|
flow control; relative and absolute addressing
|
|
|
memory addressing is used for ____, ____, ____ only
|
load store branch
|
|
|
this powerPC instruction set can provide different levels of capability, access and performance
|
processor control
|
|
|
memory control instructions give the powerPC programmer access to ____ memory, provides ____ instructions for setting and controlling various modes as well as ____ control for use with special I/O devices
|
cache memory, privileged instructions, external
|
|
|
the powerPC 7400 provides ___bit multifunctional vector execution unit
|
128
|
|
|
powerPC vector instructions can operate in ____ and provide integer and floating point arithmetic, logic functions, shifts, vector comparison, type conversion, packing and unpacking, and vector permutation capabilities
|
parallel
|
|
|
PowerPC memory addressing is used for load, store, branching only. Other instructions take their operands from _____ aka ____ mode.
|
fields within the instructions - immediate mode
|
|
|
the powerPC uses logical addressing. it uses 4 translation mechanisms for converting logical to physical:
|
ordinary
direct-store block addressing no translation |
|
|
what is ordinary translation logical addressing in a powerPC
|
divides the address into segment, page, offset
|
|
|
how is the powerPC segment (logical addressing) different to the intel segment
|
uses the segment like a super-page
|
|
|
PowerPC virtual storage divides memory into ___MB segments and divides segments into __KB pages.
|
256mb segments
4kb pages |
|
|
this powerPC logical address mode uses the segment table to perform segment translation, but the result is used directly with the remainder of the logical address to form a real address. also used in I/O addressing
|
direct-store translation
|
|
|
powerPC has ___ instructions
|
224
|
|
|
power PC word size
|
32 bits
|
|
|
this powerPC logical address mode provides means for mapping a block of logical addresses larger than a single page into a contiguous area of real memory
|
block addressing translation
|
|
|
the powerPC logical translation can be disabled, and its called
|
No Translation
|
|
|
powerPC has 2 levels of system access:
|
supervisor state and user (problem) state
|
|
|
in a powerPC, bits in the _____ _____ are used to set the state
|
system registers
|
|
|
PowerPC protects memory at the ____, _____, and ____ levels
|
segment, block and page
|
|
|
name the 3 z-series mainframes
|
s/360
s/370 s/390 |
|
|
the s/360 was introduced in ____
|
1964
|
|
|
the s/370 was introduced in ____
|
1970
|
|
|
the s370 added ____ _____ and support for ___ cpu's operating together
|
virtual storage; 2 cpu's
|
|
|
in 1981, ibm introduced the ____/__ design and added what
|
s370/XA; added more cpu's channel subsystem, and 31 bit address space
|
|
|
the s/390 has _____ __bit gp registers and __ floating point registers
|
16 64bit; 16 floating point
|
|
|
the s/390 has a ___bit program status word
|
128
|
|
|
the s/390 program status word contains the __, ___ for ___, an ___ key for cpu protection
|
program counter, mask bits for interrupts and an access key for cpu protection
|
|
|
all zseries instructions are ___, __, or __ bits in length
|
16, 32, 48
|
|
|
the length of zseries instructions are determined by ___
|
1st 2 bits in the opcode
|
|
|
in the zseries, there are __ different instruction formats depending on the operands and type of addressing used
|
18
|
|
|
zseries instructions operate between ____, ____ and ____, and ____ locations directly
|
registers, registers and memory, and memory
|
|
|
zseries divided the instructions into these 5 categories by type of operand (4 operands)
|
general, decimal, floating point, and control
|
|
|
in zseries, these instructions include data transfer,integer arith and logical ops, branches, shifts...
|
general
|
|
|
the special interupt ___ ___ is in the general instruction set in a zseries
|
supervisor call
|
|
|
these zseries instructions perform simple arith including rounding, editing, comparing, for packed decimals of varying length
|
decimal
|
|
|
operands for these zseries instructions are found in memory and do not use registers
|
decimal
|
|
|
these zseries instr include load store round normalize and compare floating point numbers and add, sub, div, mult, square root
|
floating point
|
|
|
the zseries floating point instructions work on __, __, and ___ bit formats
|
32, 64, 128
|
|
|
zseries ____ instructions are privileged and operate flags in the PSW
|
control
|
|
|
zseries defines 4 types of addressing operands:
|
immediate, register, storage, storage indexed
|
|
|
zseries immediate data is found in the ____ field of the instruction
|
immediate
|
|
|
this zseries address mode is found by adding the base register, b field of the instruction and the displacement field of the instruction
|
storage
|
|
|
this zseries address mode is similar to storage addressing, with the addition of an index value
|
indexed storage
|
|
|
the zseries index value is stored in a register indicated by an __ field in the instruction
|
x field
|
|
|
does the zseries use logical addressing?
|
yes, using a segment and page lookup table
|
|
|
zseries cpu can operate in these 2 modes
|
supervisor or problem state
|
|
|
zseries cpu provides storage access protection at the ____ ___, ____, and ____ levels
|
address space, segment and page levels
|
|
|
zseries address spaces can be completely isolated from each other
|
true
|
|
|
in zseries, the ____ stored in the PSW is used to compare against the ____ info stored for each page in order to control access to memory
|
access key
|
|
|
API stands for
|
application programming interface
|
|
|
API does what
|
provides interface with system, files, other programs
|
|
|
define OS
|
collection of computer programs that integrate hardware and make resources available to user and allows productive timely, efficiency
|
|
|
two names for starting a computer
|
bootstrapping and IPL (initial program load)
|
|
|
single-user single tasking OS
|
DOS
|
|
|
single user multi-tasking OS
|
win/home
|
|
|
multi user multitasking OS/computer
|
mainframe/epcidic
|
|
|
distributed system type
|
cluster or google
|
|
|
embedded system type
|
car/cell/low-power OS
|
|
|
real time system type
|
batch jobs
|
|
|
part of the OS that contains routines to handle interrupts manage resources and in some OS's will accept user commands
|
kernel
|
|
|
what are the 3 main memory resident components of MSDOS
|
1 cmd shell
2 I/O routines for each device connected 3 file mgt system |
|
|
bios is contained in this type of memory
|
ROM/non-volitile
|
|
|
3 files required by MSDOS
|
io.sys command.com msdos.sys
|
|
|
MSDOS supports only ____ mode addressing
|
real
|
|
|
a ____ is considered the standard unit of work within a computer system
|
process
|
|
|
processes include the program running and _____
|
the resources assigned to it
|
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the process control mgt keeps track of each process in ___, determines the state of each process and keeps track of the processes files, register info, and memory.
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memory
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what is the purpose of the memory manager
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load programs into memory and assign the memory it needs to execute
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the memory mgr has 3 tasks:
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1 keep track of memory
2 maintain queues 3 allocate/deallocate space |
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what are threads
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mini-processes
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each thread can have its own context
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true
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each thread cant have its own stack
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false
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what are the 5 process states
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1 new
2 ready 3 blocked 4 running 5 terminated |
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program scheduling is aka _____
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dispatcher
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the dispatcher can be _____ or _____
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preemptive or non-preemptive
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explain non-preemptive dispatching
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dispatcher takes control of the current running process due to blocked i/o or some other malfunction
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explain preemptive dispatching
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multitasking that uses the clock cycle to preempt the running program and make a fresh decision
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dispatchers prevent what
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starvation
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starvation can happen in this I/O mode
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SJF - shortest job first
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which scheduling technique manages i/o and then goes back to FIFO
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priority scheduling
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preemptive dispatching in its simplest forms
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round robin
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name 2 things about multilevel feedback queue
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favors short jobs
i/o bound jobs each level assigns more cpu time |
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what service handles context switching
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dispatcher
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simplest (non-preemptive) dispatching where starvation is impossible
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FIFO
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if a process has been running a long time this dispatcher scheduling technique allows other processes access
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dynamic priority scheduling
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before virtual storage, the memory mgr divided memory into
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partitions
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name the two types of memory manager partitioning
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fixed and variable partitioning
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term for when memory manager overwrites portions of memory with new code
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overlays
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windows uses a page file, unix its called
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swap partition
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system performs page swapping only when required as result of page fault
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demand paging
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system attempts to anticipate paging needs
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prepaging
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tendency of a process to execute in small areas of memory - outside where the main body of the program executes
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locality
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pages shared among different processes
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page sharing
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repeated page swapping
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thrashing
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to improve performance for page table lookups, most systems use a small amount of special memory called _______ ______
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associative memory
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ability of the OS to protect process's pages from being accessed by another program
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process separation
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endianess where MSB is on the left side
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big endian
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endianess where MSB on the right
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little endian
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name the 2 types of hard drive free space management
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bitmap and linked list
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file management system that stores data about files... attributes
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metadata layer
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name the 2 types of directory/file name structures
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tree and acyclic
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powerPC cpu and memory instructions are considered _____
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priviliged
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two types of computer clusters
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shared disk and shared nothing
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name the 4 parts of a hard drive)
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sectors, tracks, blocks (512b) cylinders
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hard drive velocity where the bits on each track are the same
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constant angular velocity
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which computer type, powerPC or x86 uses big endianess
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PowerPC
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what sector is the MBR on?
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0
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generalization representation of a file tree
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acyclic graph
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