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31 Cards in this Set
- Front
- Back
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Computer Architecture |
Specifications of a set of instructions and Specifications of the behavior of hard units to implement these instructions |
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5 Basic Units of a Computer |
Input, Output, Memory, ALU, Control |
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State the purpose of the PC Register |
PC holds the memory address, pointing to the next instruction to be fetched in the execution sequence |
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State the purpose of the IR Register |
IR holds the instruction most recently fetched from memory so that it can feed the control logic that generates appropriate control signals |
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What is instruction set architecture
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Conceptual structure and functional behavior of a computer system as seen by the assembly-language programmer; includes machine instructions and other formats, addressing models, date representation and storage organization
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3 conditions for overflow to occur |
1. inputs have the same sign
2. addition is performed 3. the output is a different sign than the inputs |
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Main difference between CISC and RISC style architectures with respect to data operands
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RISC has one word instructions and requires arithmetic operands to be in the register
CISC has multi-word instructions and allows operands directly from memory |
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How many address bits are encoded in a RISC style call |
There are 32 bits available.
For a call instruction 6 of these must be allocated to the op-code, which leaves 26 bits allocated to an immediate value that is used to determine the address of the first instruction in the subroutine. Address truncated to 26 bits by dropping least 2 significant bits and 4 most significant bits. |
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2 methods of parameter passing
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Through the stack or in registers
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Using transfer notation specify the first two steps of executing that are common to all risc-style instructions
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1. Memory address <- [PC], Read memory, IR <- Memory Data, PC <- [PC] + 4
2. Decode instructions, RA <- [RS], RB <- [RT] |
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Describe the possible sources of the data contents placed in register RY for instructions that modify a register in the programmer-visible register file |
RY is fed by a multiplexer that selects between a return address, a memory address or RZ |
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What internal hardware elements are necessary in the datapath of a basic processing unit to support the execution of a store instruction? |
Since memory access is done in stage 4 for a store operation, another inter-stage register is needed to maintain correct data flow in the multistage structure, Register RM is introduced for this purpose. The data to be stored is moved from RB to RM in step 3, and from there to memory in step 4 |
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How many transistors does an SRAM have? |
6 |
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How many transistors does a DRAM have? |
1 |
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What does SRAM stand for? |
Static- Random Access Memory |
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What does DRAM stand for? |
DYNAMIC RANDOM ACCESS MEMORY |
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What does EEPROM stand for? |
Electrically Erasable Programmable Read-Only Memory |
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Main different between an EEPROM and a flash type? |
In EEPROM it is possible to read and write to individual calls. Flash is based on EEPROM, but to allow for a higher density the flash cells must be written in larger blocks, not indivudally |
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Explain the difference in handling of address pins for SRAM and DRAM |
SRAM chips have as many pins as there are address bits, all the address bits are provided to the chip at the same time. DRAM chips have a much larger capacity but to reduce package costs the address pins are multiplexed , first row bits are provided then column bits |
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Why is the clock input included for synchronous chips |
An SRAM chip utilizes an internal column counter that is automatically incremented by the clock cycle input. Older DRAM chips relied on an external memory controller to increment the coulmn counter which is slower. |
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Identify and explain the different types of locality exploited by caches |
Temporal locality: instructions/data that have been recently accessed are likely to be accessed again Spatial locality: nearby instructions or data are likely to be accessed after current access |
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Cache memory appears to make memory appear to be __________ than it is. |
Faster |
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Virtual memory makes memory appear to be ________ than it is. |
Larger |
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If 65% of a Programs execution time can be reduced with parallel execution, write unsimplified expressions for the speedup on 4 processors and also the upper limit on the achievable speedup for this program |
fenh = 0.65 fenenh = 0.35 4 processor speed up =( 1/fenenh + fenh/p) = 1/(0.35+0.65/4) = 1.95 maximum speed up = 1/(0.35 + 0.65//∞)=1/0.35=2.86 ) |
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Parallel programming involves thread ________ and ______________ |
Parallel programming involves thread creation andsynchronization. |
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Cache Coherance |
The enforcement of a consistent view of shared data inmultiple caches, typically with a hardware solution for good performance |
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3 states for a block in a cache |
Modified, invalid, shared |
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Write initial assembler directives |
. .text .global_start .org 0x0000 _start: |
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write the Print Char subroutine |
subi sp,sp,8 stw r3,4(sp) stw r4,0(sp) movia r3,0x10001000 pc_loop: ldwio r4,4(r3) andhir4,r4,0xFFFF beqr4,r0,pc_loop stwior2,0(r3) ldwr3,4(sp) ldwr4,0(sp) addisp,sp,8 ret |
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Write the getChar subroutine |
GetChar: subi sp,sp,8 stwr3,4(sp) stwr4,0(sp) moviar3,0x10001000 gc_loop: ldwio r4,0(r3) andir2,r4,0x8000 beqr2,r0,gc_loop andir2,r4,0xFF ldwr3,4(sp) ldwr4,0(sp) addisp,sp,8 ret |
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Write the getDigit subroutine |
GetDigit: subi sp,sp,12 stwr3,8(sp) stw r4,4(sp) stw r5,0(sp) movi r3,0xA movir4,0x30 movir5,0x39 get_loop: GetChar check_loop: beqr2,r3,carriage_return blt r2,r4,get_loop bgt r2,r5,get_loop subir2,r2,0x30 br gd_exit carriage_return: movi r2,0xA gd_exit: ldwr3,8(sp) ldwr4,4(sp) ldwr5,0(sp) addisp,sp,12 ret |
