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206 Cards in this Set
- Front
- Back
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high-speed memory located in the processor used to perform arithmetic or logical functions
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Accumulator
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A measure of how our instrument measures the desired parameter referred to to NIST. (actual - ideal)/(ideal)
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Accuracy
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clearing the interrupt flag bit that requested the interrupt
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Acknowledge
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an electronic device that allows computer commands to affect the external world
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ADC
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a set of digital signals that connect the CPU, memory and I/O devices, specifying the location to read or writes for each bus cycle
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Address Bus
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the total number of possibilities. an 8-bit digital to analog converter (DAC) can generate 256 different analog outputs.
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Alternatives
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activate so that interrupts are requested
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Arm
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AKA pseudo-op
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Assembly directive
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software execution that can not be divided or interrupted.
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Atomic
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A 9S12 mode with the background debug module (BDM) active (aka interrupts)
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Background mode
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the information transfer rate, the amount of data transferred per second. (aka throughput)
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Bandwidth
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subset from which linear combinations can be used to reconstruct the entire set.
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Basis
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the total number of bits (information, overhead, and idle) per time that are transmitted
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Baud Rate
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digital signals that can be either input or output
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Bi-directional
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the ability to process numbers in both big and little endian formats
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Biendian
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mechanism for storing multiple byte numbers such that the most significant byte exists first (in the smallest memory address)
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Big endian
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a function that produces its result given two input parapets. For example, addition, subtraction, and multiplication are binary operations
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Binary Operation
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a recursive technique that makes two calls to itself during the execution of the function
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Binary Recursion
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the basic unit of time used in serial communication
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Bit time
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a software/hardware synchronization method where the software waits a specified amount of time for the hardware operation to complete. The software has no direct information (blind) about the status of the hardware
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Blind cycle
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during subtraction, if the difference is too small, then we use a borrow to pass the excess information into the next higher place. For example, in decimal subtraction 36-27 requires a borrow from the ones to tens place because 6-7 is too small to fit into the 0 to 9 range of decimal numbers.
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Borrow
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an instrument that halts the processor.
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Break/Trap
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a FIFO queue is placed in between the hardware and software in an attempt to increase bandwidth by allowing both hardware and software to run parallel.
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Buffered I/O
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the process of programming a ROM, PROM, or EEPROM
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Burn
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a software/hardware synchronization method where the software continuously reads the hardware status waiting for the hardware operation to complete.
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Busy-waiting
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establishing an upper bound on the result of an operation
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Ceiling
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a control that includes sensors to measure the current state variables. these inputs are used to drive the system to the desired state
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Closed Loop Control System
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a computer system that supports two or more software tasks that are simultaneously active. typically one task executes at a time, and there are mechanisms to suspend one tasks and execute another task. compare to parallel programming
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Concurrent programming
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register in the processor that contains the status of the previous ALU operation, as well as some operating mode flags such as the interrupt enable big
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CCR
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a set of digital signals that connect the CPU, memory, and I/O devices, specifying when to read or write for each bus cycle.
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Control Bus
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component of the processor that determines the sequence of operations
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Control Unit (CU)
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a situation where the input or output device is faster than the software.
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CPU bound
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locations within a software module, which if an interrupt were to occur at one of these locations, then an error could occur (e.g. data lost, corrupted data, program crash, etc.) aka vulnerable window
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Critical section
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an electronic device that converts digital signals (i.e, integers) to analog form (e.g. voltage)
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DAC
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Denormalizeda denormalized number is an unnormalized floating point number with an exponent of the smallest possible value. an unnormalized number has mantissa value less than one. the mantissa of a normalized floating point number is greater than or equal 1, but strictly less than 2
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Denormalized
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perform by determining in advance, either by analytical algorithm or explicit calculations, the expected outputs of strategic intermediate stages and final results for typical inputs. We then run our program and compare the actual outputs with this template of expected results
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Desk checking/dry run
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a collection of software routines that perform I/O functions.
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Device driver
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processing of data with digital hardware or software after signal has been sampled by the ADC (e.g. filters, detection and compression/decompression)
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Digital signal processing
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deactivate so that interrupts are not requested
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Disarm
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software/hardware synchronization method where the hardware itself causes a data transfer between the I/O device and memory at the appropriate time when data needs to be transferred. the software usually can perform other work while waiting for the hardware. no software action is required for each individual byte
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Direct Memory Access (DMA)
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two separate and complete switches that are activated together
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double-pole switch
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a switch with three contact connections. the center contact will be connected exactly one of the other two contacts
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double-throw switch
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an error that occurs after a right shift or a divide, and the consequence is that an intermediate result looses its ability to represent all of the values
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drop out
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a computer bus cycle that fetches data pointed to by the SP, but the data is not used
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dummy PC
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a computer bus cycle that fetches data pointed to by the SP, but the data is not used
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dummy SP
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for a periodic digital wave, it is the percentage of time the signal is high
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duty cycle
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electrically erasable programmable read only memory that is nonvolatile and easy to reprogram. typically, can be erased and reprogrammed over 10,000 times
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EEPROM
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a register that contains the address for the current memory cycle
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effective address register (EAR)
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a system that performs a specific dedicated operation where the computer is hidden or embedded inside the machine
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embedded computer system
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memory that is nonvolatile and requires external devices to erase and reprogram. it is usually erased using UV light.
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EPROM (electrically programmable read only memory)
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a communication protocol where the number of ones in the data plus a parity bit is an even number.
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even parity
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the mode where some of the I/O ports are used to create an external data bus (control, address, data) allowing external memory to be connected
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expanded mode
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an addressing mode where the data or address value for the instruction is located anywhere in memory
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extended
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the number of inputs that a single output can drive if the devices are all in the same logic family
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fan out
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a 9S12 mode where the associated flag is automatically cleared when the data or timer register is accessed
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fast clear
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a boolean function or conditional test used to make run-time decisions
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filter
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a technique where calculations involving non integers are performed using a sequence of integer operations
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fixed-point
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memory that is nonvolatile and easy to reprogram. has fewer erase-reprogram cycles
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flash EEPROM
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a loci state where the output device does not drive high or pull low. the outputs of open collector and tristate devices can be in the floating state
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floating (aka HiZ)
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establishing a lower bound on the result of an operation
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floor
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used in parallel programming to create additional software tasks that will run in parallel
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fork
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a complete and distinct packet of bits occurring in a serial communication channel
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frame
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an error when the receiver expects a stop bit (1) and the input is 0
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framing error
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when software modifies just the bits that need to be modified, leaving the other bits unchanged
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friendly
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the process of detecting, locating, or correcting functional and logical errors in a program and the process of instrumenting a program for such purposes
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functional debugging
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as one that can guarantee that a process will complete a critical task within a certain specified range. In data acquisition system this means there is an upper bound on the latency between when a sample is supposed to be take (every 1/fs) and when the ADC converter is actually started. also implies that no ADC samples are missed
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hard real-time system
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when latching data into a device with a rising or falling edge of a clock, this is the time after the active edge of the clock that the data must continue to be valid.
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hold time
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a situation where the input or output device is slower than the software
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I/O bound
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a computer component capable of bringing information from the external environment into the computer, or sending data out from the computer to the external environment
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I/O device
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a hardware device that connects the computer with external components
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I/O port
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an addressing mode where the operand is fixed data or an address value
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immediate
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a control system where the actuator has many possible states, and the system increments or decrements the actuator value depending on either in error is positive or negative
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incremental control system
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an addressing mode where the data or address value for the instruction is located in memory pointed to by an index register
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indexed
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an addressing mode where there is no operand or where the operand is implied
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inherent
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register in the control unit that contains the op code for the current instruction
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instruction register (IR)
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the process of injecting of inserting a debugging instrument
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instrumentation
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a software/hardware synchronization method where the hardware causes a special software program to execute when its operation to complete. the software usually can perform other work while waiting for the hardware
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interrupt
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a status bit that is set by the hardware to signify an external event has occurred
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interrupt flag
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a control bit that, if programmed to 1, will cause an interrupt request when the associated trigger float is set
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interrupt mask (aka arm)
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program that runs as a result of an interrupt
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interrupt service routine (ISR)
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16-bit values at the end of memory specifying where the software should execute after an interrupt request.
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interrupt vector
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used in parallel programming to combine two or more software task into one. execution after a join will continue when all software task above it are complete
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join
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as a noun, it means a register. as a verb, it means to store data into the register
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latch
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an input port where the signals are saved on an edge of an associated strobe signal
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latched input port
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refers to the response time of the computer to external events
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latency
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mechanism for storing multiple byte numbers such that the least significant byte exists first (in the smallest memory address)
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little endian
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system software that places the object code into the microcomputer's memory
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loader
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process of verifying, changing, correcting, enhancing, and extending a system
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maintenance
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as a verb, the operation that selects certain bits out of many bits, using the logical and operation. as a noun, it refers to the specific bits that are being selected
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mask
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a signal measured by a data acquisition system
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measurand
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the symbolic name of an operation code, like ldaa psha stx
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mnemonic
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a signal where the true value has a lower voltage than the false value
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negative logic
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a characteristic when the presence of the collection of information itself does not affect the parameters being measured
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nonintrusive
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the characteristic or quality of a debugger that makes the order of invocation immaterial
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noninvasive
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a software module that once started by one thread, can not be interrupted and executed by a second thread. usually involve non atomic accesses to global variables or I/O ports
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nonreentrant
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a condition where the information is not lost when power is removed
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nonvolatile
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read/write storage that achieves its long term storage ability because it includes a battery
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nonvolatile RAM
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the mantissa of a normalized floating point number is greater than or equal to 1, but strictly less than 2
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normalized
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a computer bus cycle that fetches data at address $FFFF, but the data is not used
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null cycle
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If an input signal is captured by an ADC at the regular rate of fs samples/sec, then the digital sequence will accurately represent the 0 to 0.5 fs frequency components of the original signal.
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Nyquist Theorem
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programs in machine readable format created by the compiler or assembler.
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object code
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a communication protocol where the number of ones in the data plus a parity bit is an odd number
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odd parity
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a specific instruction executed by the computer
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op code
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a digital logic output that has two states low and HiZ
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open collector
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a control system that does not include sensors to measure the current state variables
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open loop control system
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the second part of an instruction that specifies either the data or the address for the instruction
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operand
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system software for managing computer resources and facilitating common functions like input/output, memory management, and file system.
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operating system
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a hardware debugging tool that allows you to visualize one or two analog signals versus time
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oscilloscope
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a mechanism to cause a flag to be set and an output pin to change when the TCNT matches a preset value. can also request an interrupt
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output compare
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an error that occurs when the result of a calculation exceeds the range of the number system
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overflow
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an error that occurs when the receiver gets a new frame but the data register and shift register already have information
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overrun error
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a por there all signals are available simultaneously
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parallel port
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a computer system that supports simultaneous execution of two or more software tasks
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parallel programming
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an addressing mode where the effective address is calculated by its position relative to the current value of the program counter
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PC relative
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the process of acquiring or modifying timing characteristics and execution patterns of a program and the process of instrumenting a program for such purposes
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performance debugging or profiling
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a software/hardware synchronization method that is a combination of interrupts and busy-waiting
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periodic polling
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a software function to look and see which of the potential sources requested the interrupt
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polling
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external pins through which the microcomputer can perform input/output
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port
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a signal where the true value has a higher voltage than the false value
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positive logic
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for an input signal, it is the number of distinguishable input signals that can be reliably detected by the measurement. for an output signal, it is the number of different output parameters that can be produced by the system
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precision
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a shorthand for describing a software algorithm
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pseudo-code
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a variable that is shared by multiple programs or threads
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public variable
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a type of memory where the information can be stored and retrieved easily and quickly. since it's volatile, the information is lost when power is removed
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RAM (random access memory)
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includes both the smaller possible and the larger possible signal (input or output)
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range
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Range formula
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Precision*Resolution
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a system that can guarantee an upper bound (worst case) on latency
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real-time
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a system where time-critical operations occur when needed
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real-time computer system
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a programming technique where a function calls itself
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recursion
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a software module that can be started by one thread, interrupted and executed by a second thread.
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reentrant
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high-speed memory located in the processor
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registers
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a parameter specifying low consistent over time the measurement is when the input remains fixed
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reproducibility (or repeatability)
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the 16-bit value at memory locations $FFFE and $FFFF specifying where the software should start after power is turned on or after a hardware reset
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reset vector
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for an input signal, it is the smallest change in the input parameter that can be reliably detected by the measurement. for an output signal, it is the smallest change in the output parameter that can be produced by the system.
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resolution
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software, usually executed once at the beginning of the program, which defines the operational modes of the I/O ports
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ritual
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a type of memory where the information is programmed into the device once, but can be accessed quickly. it is low cost, must be purchase in high volume and can be programmed only once
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ROM (read only memory)
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the error that occurs in a fixed-point or floating-point calculation when the least significant bits of an intermediate calculation are discarded so the result can fit into the finite precision
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roundoff
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the rate at which data is collected in a data acquisition system
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sampling rate
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any instrument used to produce a side effect without causing a break
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scan/scan point
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the slope of the output versus input response
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sensitivity
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a process where information is transmitted one bit at a time
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serial communication
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a device to transmit data with asynchronous serial communication protocol
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serial communications interface (SCI, ask UART or ACIA)
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device to transmit data with synchronous serial communication protocol
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serial peripheral interface (SPI)
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an I/O port where the bits are input or output one at a time
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serial port
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when latching data into a device with a reusing or falling edge of a clock, it is the time before the active edge the active edge of the clock that the data must be valid
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setup time
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a software application which simulates or mimics the operation of a processor or computer system
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simulator
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programs in human readable format created with an editor
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source code
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a digital value of false or logic 0
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space
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the relative sensitivity of the device to the signal of interest versus the sensitivity of the device to other unwanted signals.
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specificity
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involves specifying all its inputs
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stabilize
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last in first out data structure located in RAM and used to temporarily save information
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stack
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a register in the processor that points to the RAM location of the stack
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stack pointer (SP)
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overhead bit(s) specifying the beginning of the frame, used in serial communication to synchronize the receiver shift register with the transmitter clock
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start bit
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volatile read/write storage built from three transistors having fast speed, and not requiring refresh
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static RAM
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a motor that moves in discrete steps
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stepper motor
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overhead bit(s) specifying the end of the frame, used in serial communication to separate one frame from the next
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stop bit
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the execution of software that cooperates with others of its kind. embodies the action of the software. the sequence of operations including the input and output data
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thread
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change 0 to 1 or 1 to 0
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toggle
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a device that converts one type of signal into another type
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transducer
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the hardware and software are tightly coupled so that both wait for each other during the transmission of data
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unbuffered I/O
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an address at the end of memory containing the location of the interrupt service routines
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vector
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a condition where information is lost when power is removed
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volatile
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clra
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inherent
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ldaa #36
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immediate
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ldaa $32
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direct
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ldaa $3800
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extended
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ldaa,0,X
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indexed
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bra main
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PC relative
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movb #w,addr
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extended, immediate
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movb addr1, addr2
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extended-extended
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component of the processor that reads and writes data from the bus; controls the address and data bus connections to the memory
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bus interface unit (BIU)
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a function parameter that contains the data itself
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call by value
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the process of converting a 16-bit integer into an 8-bit integer
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demotion
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promotion
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the process of converting an 8-bit integer into a 16-bit integer
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a characteristic of a debugger when the presence of the collection of information itself makes a small but unimportant effect on the parameters being measure
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minimally intrusive
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2^0
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1
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2^1
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2
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2^2
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4
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2^3
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8
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2^4
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16
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2^5
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32
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2^6
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64
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2^7
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128
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2^8
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256
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2^9
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512
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2^10
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1,024
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2^11
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2,048
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2^12
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4,096
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2^13
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8,192
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2^14
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16,384
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2^15
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32,768
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2^16
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65,536
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I/O Ports:
Address and Contents |
Address:
$0000 to $03FF Contents: Access external devices |
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EEPROM:
Address and Contents |
Address:
$0400 to $07FF Contents: Fixed constants |
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RAM:
Address and Contents |
Address:
$0800 to $3FFF Contents: Variables and stack |
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EEPROM:
More Address and Contents |
Address:
$4000 to $FFFF Contents: Programs and fixed constants |
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PHASE 1a
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Function: Op code fetch
R/W: read Address: PC++ Comment: put op code into IR |
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PHASE 1b
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Function: Operand fetch
R/W: read Address: PC++ Comment: immediate or calculate EA |
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PHASE 2
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Function: Decode instruction
R/W: none Address: same? Comment: figure out what to do |
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PHASE 3
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Function: Evaluation address
R/W: none Address: same Comment: determine EAR |
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PHASE 4
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Function: Data read
R/W: read Address: SP,EAR Comment: Data passes through ALU |
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PHASE 5
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Function: free cycle
R/W: read Address: PC/SP/$FFFF Comment: ALU operations, set CCR |
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PHASE 6
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Function: data store
R/W: write Address: SP,EAR Comment: Results stored in memory |
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Orchestrates the sequence of operations in the processor
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Control Unit (CU)
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How to calculate LED resistance
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R = (5-Vd-Vol)/Id
Vd,Id is desired LED operating point Vol is the output low voltage of the LED driver |
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the number of distinct or different values (expressed in alternatives, decimal digits, bytes, or binary bits)
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precision
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the total number of possibilities
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alternatives
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