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25 Cards in this Set

  • Front
  • Back
Define Instrution Set Architecture(ISA).
It is an abstract inerface between the hardware and the lowest level software.
Give the two main advantages of a multiple clock cycle implementation of the MIPS processorover a single clock cycle implementation.
1. uses the clock cycle efficiently

2. faster clock rate
Does the pipelining reduce an instructions's latency?
Cache memories are usually made of of SRAM's, why?
SRAM is faster.
Main memories are usually made out of DRAM's, why?
DRAM has higher density, even though it is slower.
What is the goal of having a memory hiearchy?
Improve performance by taking advantage of temporal locality and spatial locality.
Why do caches usually have write buffers?
on a write miss, writes to memory woud slow the pipeline down. so write buffers are used to so that you only have to stall the pipeling when the buffer is full instead of every time you want to write
Average Access Time =
miss rate * miss penalty + hit time
Give an example of an external interrupt event.
request from I/O device
Give an example of an inernal trap event.
arithmatic overflow
Single cycle processor takes how many nanoseconds per instruction?
Each clock cycle takes how many nanoseconds?
bandwidth =
byte/clock cycle
One word blocks take advantage of what type of locality?
Temporal locality
Multi-word blocks take advantage of what type of locality?
Spatial locality
Name the three sources of cache misses?
1. Compulsory misses
2. Capacity misses
3. Conflict misses
Give the two methods used to address I/O devices.
1. special I/O instructions
2. memory mapped I/O
Give an advantage and disadvantage of a single bus.
advantage - low cost
disadvantage - communication bottleneck
Name the bus arbitration scheme described in class and complete the block diagram illustrating it with three I/O devices.
single master arbitrator
Name the two types of buses.
1. Synchronous
2. Asynchronous
Name and advantage and disadvantage of Synchronous buses.
advantage - involves very little logic, so it can run fast

disadvantage - every device must run at the same clock time
Name and advantage and disadvantage of Asynchronous buses.
advantage - can accommodate a wide range of devices

disadvantage - slow
In a multi-cycle processor tell how many clock cycles the following instructions take:
lw, add, sw, j, beq,
lw - 5
add - 4
sw - 4
j - 3
beq - 3
3 pipeline hazards and describe them
structural - attempt to use the same resource by two
different instructions at the same time

data - instruction depends on result of prior instruction still in the

control hazards - attempt to make a decision before condition is evaulated (branch instructions)
Define temporal and spatial locality.
temporal - Keep most recently accessed data items closer to the processor

spatial - Move blocks consisting
of contiguous words
to the upper levels