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63 Cards in this Set

  • Front
  • Back
A computer designed for use by an individual, usually incorporating a graphics display keyboard and a mouse
A computer used for running larger programs for multiple users often simultaneosly and typically accessed only via a network
Embedded computer
A computer inside another device used for running one predetermined application or collection of software
What components affect performance?
Algorithm. Programming language, compiler and architecture. Processor and memory system. I/O system (hardware and operating system)
How does the algorithm affect performance?
Determines both the number of source-level statements and the number of I/O operations executed
How do the Programming language, compiler and architecture affect performance?
Determines the number of machine instructions for each source-level statement
How do the Processor and memory system affect performance?
Determines how fast instructions can be executed
How does the I/O system affect performance?
Determines how fast I/O operations may be executed
Main components of the computer and examples
Compiler(gcc), I/O(mouse and monitor), Control/Datapath, Memory(RAM), CPU(Intel chip)
The component of the processor that performs arithmetic operations
The component of the processor that commands the datapath, memory, and I/O devices according to the instructions of the program
A model that renders lower level details of computer systems temporarily invisible in order to facilitate design sophisticated systems
A value used to delineate the location of specific data element within a memory array.
Translate into MIPS

A[12] = h + A[8]

lw $t0, 32($s3) #temp reg $t0 get A[8], alignment restriction, word = 4

add $t0, $s2, $t0 #g= h + A[8]
sw $t0,48($s3)
Spilling Registers
The process of putting less commonly used variables (or those needed later) into memory
Design Principles
Simplicity favors regularity.
Smaller is faster.
Make the common case fast.
Good design demands good compromises.
Mips fields for R-format in order and bits
op - 6, rs - 5, rt - 5, rd - 5, shamt - 5, funct - 6
add, sub, and, or, nor, sll, srl, slt
Mips fields for I-format in order and bits
op - 6, rs - 5, rt - 5, constant address - 16
addi, lw, sw, andi, ori, beq, bne
the field that denotes the operation of an instruction
shift amount
What does shift left by i bits do?
multiplies by 2^i
Mips fields for J-format in order and bits
op - 6, target address 26
jumps to an address and simultaneously saves the address of the following instruction in $ra
frame pointer
A value denoting the location of the saved registers and local variables for a given procedure
set the upper 16 bits of a constant in a register allowing a subsequent instruction to specify the lower 16 bits of the constant
factorial program
fact: addi sp sp 8, sw ra 4sp, sw a0 0sp, slti t0 a0 1, beq t0 zero L1, addi v0 zero 1, addi sp sp 8, jr ra. L1: addi a0 a0 -1, jal fact. ra: lw a0, 0sp, lw ra 4sp, addi sp sp 8.
Register addressing
where the operand is a register, jr
Base or displacement addressing and where
Where the operand is at the memory location whose address is the sum of a register and a constant in the instruction
load and store
Immediate addressing
where the operand is a constant within the instruction itself, for addi, lui,... op, rs, rt, imm
PC-relative addressing and where
where the address is the sum of the PC and a constant in the instruction

Pseudodirect addressing
where the jump address is the 26 bits of the instruction shifted left 2 concatenated with the upper 4 bits of the PC
Assembly Language
a symbolic language that can be translated into binary
Machine Language
Binary representation used for communication within a computer system
Jump address table
case/switch. A table of addresses of alternative instruction sequences
Least sig bit
the rightmost bit in a MIPS word
Most sig bit
the leftmost bit in a MIPS word
2's compliment
first bit is sign bit, if 1 take 2's compliment of number and put neg in front. -2^31 has no pos number.
floating point register single
s - 1, exp - 8, fraction - 23
floating point register double
s - 1, exp - 11, fraction - 52
overflow fp
a situation in which a pos exp becomes too large to fit in the exp field
underflow fp
a situation in which a neg exp becomes too large to fit in the exp field
IEEE 754
significand represents the 24/53 bit number. while fraction(not IEEE 754) uses 23/52
-1^s x (1 + fraction) x 2^E-bias
why is the sign bit important in IEEE 754
It allows for a quick test of less than, greater than, equal to 0.
biased notation
the bias is the number subtracted from the normal, unsigned representation to determine the real value. to simplify sorting. bias = 127 single, 1023 double
execution time def
The total time required for the computer to complete a task, including disk accesses, memory acceses, I/O activites, operating system overhead, CPU execution time and so on
Perfomance =
1/Execution time
clock cycle/period
The time for one clock period, usually of the processor clock, which runs at a constant rate
CPU execution time
cpu clock cycle x clock cycle time or clock cycle/clock rate

clock cycle = CPI x IC
clock cycles
sum of CPIi x Ii
Ways to increase CPU performance
increase clock rate.
improve processor organization to lower CPI.
enhancements that lower the instruction count or generate instructions with a lower average CPI
IC/(Execution time x 10^6)
Major functional units in a single cycle datapath, in order
PC(2 adders). Instruction memory. Register file. ALU. Data Memory.
Why must single cycle dps have separate instruction and data memories
1.the format of data and instructions is different in MIPS and hence different memories are needed.
2. having separate memories is less expensive.
3. the processor operates in one cycle and cannot use a single-ported memory for two different accesses within that cycle.
Clocking methodology
The approach used to determine when data is valid and stable relative to the clock.
Control signals
RegDst, RegWrite, ALUSrc, PCSrc, MemRead, MemWrite, MemtoReg
MUX to Write Register
0 - rt
1 - 15-11, rd
to Register file
assert-the register on the write register input is written with the value on the Write data input
Mux to ALU
0-read data 2(rt)
1-sign extend 15:0
branch AND zero
0 - PC + 4
1 - branch address
into data memory
assert-Data memory contents designated by the address input are put on the Read data output
data memory
assert-data memory contents designated by the address input are replaced by the value on the Write data input.

for sw
MUX to write data
0-ALU result(r type)
1-read data(address) loads
CPU execution time
CPI x I /clock rate or x clock cycle time, for single cycle CPI = 1