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63 Cards in this Set
- Front
- Back
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Desktop
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A computer designed for use by an individual, usually incorporating a graphics display keyboard and a mouse
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Server
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A computer used for running larger programs for multiple users often simultaneosly and typically accessed only via a network
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Embedded computer
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A computer inside another device used for running one predetermined application or collection of software
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What components affect performance?
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Algorithm. Programming language, compiler and architecture. Processor and memory system. I/O system (hardware and operating system)
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How does the algorithm affect performance?
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Determines both the number of source-level statements and the number of I/O operations executed
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How do the Programming language, compiler and architecture affect performance?
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Determines the number of machine instructions for each source-level statement
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How do the Processor and memory system affect performance?
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Determines how fast instructions can be executed
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How does the I/O system affect performance?
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Determines how fast I/O operations may be executed
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Main components of the computer and examples
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Compiler(gcc), I/O(mouse and monitor), Control/Datapath, Memory(RAM), CPU(Intel chip)
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Datapath
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The component of the processor that performs arithmetic operations
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Control
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The component of the processor that commands the datapath, memory, and I/O devices according to the instructions of the program
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Abstraction
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A model that renders lower level details of computer systems temporarily invisible in order to facilitate design sophisticated systems
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Address
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A value used to delineate the location of specific data element within a memory array.
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Translate into MIPS
A[12] = h + A[8] why? |
lw $t0, 32($s3) #temp reg $t0 get A[8], alignment restriction, word = 4
add $t0, $s2, $t0 #g= h + A[8] sw $t0,48($s3) |
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Spilling Registers
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The process of putting less commonly used variables (or those needed later) into memory
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Design Principles
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Simplicity favors regularity.
Smaller is faster. Make the common case fast. Good design demands good compromises. |
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Mips fields for R-format in order and bits
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op - 6, rs - 5, rt - 5, rd - 5, shamt - 5, funct - 6
add, sub, and, or, nor, sll, srl, slt |
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Mips fields for I-format in order and bits
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op - 6, rs - 5, rt - 5, constant address - 16
addi, lw, sw, andi, ori, beq, bne |
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opcode
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the field that denotes the operation of an instruction
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shamt
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shift amount
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What does shift left by i bits do?
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multiplies by 2^i
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Mips fields for J-format in order and bits
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op - 6, target address 26
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jal
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jumps to an address and simultaneously saves the address of the following instruction in $ra
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frame pointer
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A value denoting the location of the saved registers and local variables for a given procedure
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lui
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set the upper 16 bits of a constant in a register allowing a subsequent instruction to specify the lower 16 bits of the constant
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factorial program
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fact: addi sp sp 8, sw ra 4sp, sw a0 0sp, slti t0 a0 1, beq t0 zero L1, addi v0 zero 1, addi sp sp 8, jr ra. L1: addi a0 a0 -1, jal fact. ra: lw a0, 0sp, lw ra 4sp, addi sp sp 8.
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Register addressing
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where the operand is a register, jr
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Base or displacement addressing and where
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Where the operand is at the memory location whose address is the sum of a register and a constant in the instruction
load and store |
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Immediate addressing
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where the operand is a constant within the instruction itself, for addi, lui,... op, rs, rt, imm
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PC-relative addressing and where
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where the address is the sum of the PC and a constant in the instruction
BRANCHES |
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Pseudodirect addressing
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where the jump address is the 26 bits of the instruction shifted left 2 concatenated with the upper 4 bits of the PC
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Assembly Language
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a symbolic language that can be translated into binary
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Machine Language
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Binary representation used for communication within a computer system
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Jump address table
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case/switch. A table of addresses of alternative instruction sequences
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Least sig bit
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the rightmost bit in a MIPS word
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Most sig bit
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the leftmost bit in a MIPS word
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2's compliment
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first bit is sign bit, if 1 take 2's compliment of number and put neg in front. -2^31 has no pos number.
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floating point register single
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s - 1, exp - 8, fraction - 23
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floating point register double
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s - 1, exp - 11, fraction - 52
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overflow fp
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a situation in which a pos exp becomes too large to fit in the exp field
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underflow fp
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a situation in which a neg exp becomes too large to fit in the exp field
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IEEE 754
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significand represents the 24/53 bit number. while fraction(not IEEE 754) uses 23/52
-1^s x (1 + fraction) x 2^E-bias |
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why is the sign bit important in IEEE 754
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It allows for a quick test of less than, greater than, equal to 0.
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biased notation
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the bias is the number subtracted from the normal, unsigned representation to determine the real value. to simplify sorting. bias = 127 single, 1023 double
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execution time def
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The total time required for the computer to complete a task, including disk accesses, memory acceses, I/O activites, operating system overhead, CPU execution time and so on
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Perfomance =
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1/Execution time
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clock cycle/period
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The time for one clock period, usually of the processor clock, which runs at a constant rate
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CPU execution time
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cpu clock cycle x clock cycle time or clock cycle/clock rate
clock cycle = CPI x IC |
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clock cycles
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sum of CPIi x Ii
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Ways to increase CPU performance
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increase clock rate.
improve processor organization to lower CPI. enhancements that lower the instruction count or generate instructions with a lower average CPI |
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MIPS =
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IC/(Execution time x 10^6)
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Major functional units in a single cycle datapath, in order
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PC(2 adders). Instruction memory. Register file. ALU. Data Memory.
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Why must single cycle dps have separate instruction and data memories
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1.the format of data and instructions is different in MIPS and hence different memories are needed.
2. having separate memories is less expensive. 3. the processor operates in one cycle and cannot use a single-ported memory for two different accesses within that cycle. |
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Clocking methodology
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The approach used to determine when data is valid and stable relative to the clock.
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Control signals
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RegDst, RegWrite, ALUSrc, PCSrc, MemRead, MemWrite, MemtoReg
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RegDst
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MUX to Write Register
0 - rt 1 - 15-11, rd |
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RegWrite
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to Register file
deassert-none assert-the register on the write register input is written with the value on the Write data input |
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ALUSrc
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Mux to ALU
0-read data 2(rt) 1-sign extend 15:0 |
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PCSrc
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branch AND zero
0 - PC + 4 1 - branch address |
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MemRead
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into data memory
deassert-none assert-Data memory contents designated by the address input are put on the Read data output |
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MemWrite
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data memory
deassert-none assert-data memory contents designated by the address input are replaced by the value on the Write data input. for sw |
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MemtoReg
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MUX to write data
0-ALU result(r type) 1-read data(address) loads |
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CPU execution time
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CPI x I /clock rate or x clock cycle time, for single cycle CPI = 1
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