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34 Cards in this Set
- Front
- Back
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You have available 512K x 4 bit memory integrated circuits. You need a 4M x 32 bit memory system. How many address lines do you need for the memory system? How many address lines are connected the decoder? |
3-bit decoder22 address lines |
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The ripple carry adder has as one of its failings is slow since the carry has to propgate from the least significant to most significant bit position. How can the addition function be made faster? |
CLA Method: Carry lookahead method |
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Memory blocks (lines) can be mapped into cache blocks using direct mapping. How is this mapping calculated? |
%n (modulus n), n = number of blocks |
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How is it determined which DMA device has access to the computer bus? |
Arbitration, using rotation or priority schemas |
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Cache memory blocks can be mapped from main memory to cache using associative mapping. What is a disadvantage of this mapping technique? |
Complex circuitry needed to compare the tags in parallel in the cache |
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In an associative cache memory how do we determine if a cache line in the cache corresponds to the memory address presented? |
Parallel search of TAG |
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For the memory system which has 4M words of main memory, a cache of 128K words where the cache is organized as a 2 way set associative cache with a block size of 64 words, how many bits are there in the TAG, SET, and WORD fields? |
TAG = M-(SET+WORD), SET = K-(w+W), WORD = W, TAG+SET+WORD = MTAG = 6, SET = 10, WORD = 6 |
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The memory system was treated as a hierarchy of different types of memory. Which of these types is the fastest (has the shortest access time)? |
Registers |
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Of the compression techniques discussed in class, which would be used to compress a source file? Why? |
Huffman Encoding (lossless compression): zero loss of any information |
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Define hit rate as regards to cache memory operations. |
% of information that is in the cache, compared to the total information (always <= 1) |
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Memory was classified as static vs. dynamic, or volatile vs. non-volatile. Define one of the classifications. |
Static: expensive, faster memoryDynamic: cheaper, slower memoryVolatile: will lose data after being powered offNon-volatile: will retain data after being powered off |
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What is the major difference between the branch and branch and link instructions? |
Branch: no memory, no returnBranch & Link: memory, can return |
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In a pipelined architecture, why should branch instructions be avoided in writing programs? |
Branch delays/penalties: waste clock cycles on useless instructions |
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Direct Memory Access (DMA) is used with high speed I/O devices. Why is this an advantage? |
Access memory directly, bypass the processor |
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When using the one bit shift/add multiplication hardware it is only capable of multiplying two positive binary numbers and cannot multiply signed binary numbers and produce the correct signed result. What is one solution to multiply signed binary numbers? |
Booth's Algorithm |
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Who maintains the PCI bus interface standard? |
SIG |
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In the naïve implementation of a virtual memory system, the mapping of the logical (virtual) address to a physical main memory address is done with a lookup table in memory. How can this be done faster? |
TLB: translational lookaside buffer |
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Who maintains the USB interface standard? |
IEEE |
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Who maintains the Firewire interconnection standard? |
Apple (inventors), IEEE |
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How are the control signals necessary for the BPU to operate generated? |
Control unit – Hardwired, or Microprogrammed |
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If the requirement is to send data over a long distance what type of external input/output is used? |
Serial Transmission Speed |
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When accessing memory how does the BPU know when the data is available? |
Control signal from memory (MFC) |
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Define access time for memory. |
The time between address presentation and the data available |
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When simultaneous interrupt requests occur what is one method to determine which request to service first? |
Polling |
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When responding to an interrupt request how does the BPU know where the service routine is located (one method)? |
A vector points to the location of the ISR (vector interrupt scheme) |
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When calling a subroutine (also known as a function or method) describe one method to pass the parameters to the subroutine. |
By value (no change to original) |
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When shifting a register to the right what is the difference between a logical shift and an arithmetic shift? |
Logical: insert 0's at the left endArithmetic: copy sign at the left end |
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The BPU has four condition status bits which are affected by operations in the ALU. Describe what two of them indicate. |
Negative: result is negativeZero: result has no 1's |
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The ARM instruction set has instructions for three of the four integer arithmetic functions. Which one of the four is not supported by the hardware? |
Division |
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Discuss one aspect between RISC and CISC architectures that distinguishes one from the other. |
RISC: simple instructionsCISC: complex instructions |
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Given the contents of an 8 bit register in binary, what is the result in the register when logically shifting three bits right: 11000101 ? |
00011000 |
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When performing input/output how does the device recognize that the BPU is accessing it? |
The decoder on the address lines |
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What is one disadvantage of memory mapped I/O addressing? |
Possibility of a very large decoder |
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What is the advantage of using programmed (polled) I/O? |
Simple Hardware/Software |
