Reading...
Play button
Play button
Use LEFT and RIGHT arrow keys to navigate between flashcards;
Use UP and DOWN arrow keys to flip the card;
H to show hint;
A reads text to speech;
8 Cards in this Set
- Front
- Back
|
Requisite conditions for deadlock
|
1. Mutual exclusion - Each resource is either currently assign ed to exactly one process or is available.
2. Hold and wait condition - Processes currently holding resources that were granted earlier can request new resources. 3. No preemption condition. Resources previously granted cannot be forcibly taken away from a process. They must be explicitly releas ed by the process holding them. 4. Circular wait condition. There must be a circular chain of two or more processes, each of which is waiting for a resource held by the next member of the chain. |
|
|
Type of deadlock other than resource?
Solution? |
Communication deadlock
Solved with timeouts. |
|
|
7 ISO layers
|
OSI model
7. Application layer NNTP · SIP · SSI · DNS · FTP · Gopher · HTTP · NFS · NTP · SMPP · SMTP · SNMP · Telnet · DHCP · Netconf · RTP · SPDY · (more) 6. Presentation layer MIME · XDR · TLS · SSL 5. Session layer Named pipe · NetBIOS · SAP · PPTP · SOCKS 4. Transport layer TCP · UDP · SCTP · DCCP · SPX 3. Network layer IP (IPv4, IPv6) · ICMP · IPsec · IGMP · IPX · AppleTalk · X.25 2. Data link layer ATM · SDLC · HDLC · ARP · CSLIP · SLIP · GFP · PLIP · IEEE 802.2 · LLC · L2TP · IEEE 802.3 · Frame Relay · ITU-T G.hn DLL · PPP · Network switch 1. Physical layer EIA/TIA-232 · EIA/TIA-449 · ITU-T V-Series · I.430 · I.431 · POTS · PDH · SONET/SDH · PON · OTN · DSL · IEEE 802.3 · IEEE 802.11 · IEEE 802.15 · IEEE 802.16 · IEEE 1394 · ITU-T G.hn PHY · USB · Bluetooth · Hubs |
|
|
What is a memory barrier (a.k.a., memory fence)?
|
A class of instruction which causes a central processing unit (CPU) or compiler to enforce an ordering constraint on memory operations issued before and after the barrier instruction. Memory barriers are low-level primitives which are part of the definition of an architecture's memory model.
|
|
|
What is priority inversion?
|
It is a problematic scenario in scheduling when a higher priority task is indirectly preempted by a lower priority task effectively "inverting" the relative priorities of the two tasks.
This violates the priority model that high priority tasks can only be prevented from running by higher priority tasks and briefly by low priority tasks which will quickly complete their use of a resource shared by the high and low priority tasks. |
|
|
What are three possible solutions to priority inversion?
|
- Disabling all interrupts to protect critical sections
- A priority ceiling - Priority inheritance |
|
|
What is a priority ceiling?
|
With priority ceilings, the shared mutex process (that runs the operating system code) has a characteristic (high) priority of its own, which is assigned to the task locking the mutex. This works well, provided the other high priority task(s) that tries to access the mutex does not have a priority higher than the ceiling priority.
|
|
|
What is priority inheritance?
|
Under the policy of priority inheritance, whenever a high priority task has to wait for some resource shared with an executing low priority task, the low priority task is temporarily assigned the priority of the highest waiting priority task for the duration of its own use of the shared resource, thus keeping medium priority tasks from pre-empting the (originally) low priority task, and thereby affecting the waiting high priority task as well. Once the resource is released, the low priority task continues at its original priority level.
|
