Computer Science: Section 5

Front 1

Address bus

Back 1

Sent to memory to access a particular main memory location.

Front 2

Data bus

Back 2

Data in location is then returned to the CPU

Front 3

Control bus

Back 3

Carries control signals.

Front 4

Width of data bus

Back 4

Determines overall system performance.

Front 5

Width of address bus

Back 5

Determines the maximum possible memory capacity of a system.

Front 6

I/O controllers

Back 6

A device that interfaces between an input/output device and the processor. Receives signals from P and executes them on D.

Front 7

Stored Program Concept

Back 7

Machine code instructions fetched and executed serially by a processor.

Front 8

Fetch-Execute Cycle

Back 8

Address copied from PC to MAR and is sent via address bus to main memory

Instruction returned along data bus to MBR

Contents are then copied to CIR

Instruction is decided and split into opcode and operand.

ALU is used to execute the instruction and the result is stored in the accumulator or memory.

Front 9

Opcode

Back 9

The basic operation to be performed (binary)

Front 10

Operand

Back 10

Specified the data to be processed.

Front 11

Addressing mode

Back 11

Specifies how to calculate the effective memory address of an operand using memory from registers.

Front 12

Immediate addressing

Back 12

Operand is the actual value to be operated on

Front 13

Direct addressing

Back 13

The operand holds the memory address of the value to be operated on.

Front 14

Instruction set

Back 14

Complete set of all instructions in machine code that can be recognised and executed by a CPU.