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25 Cards in this Set
- Front
- Back
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Control Unit |
- The part of the processor that co-ordinates the activity of all other components. |
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Buses |
- Buses in a computer consist of a series of connectors that transfer signals |
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Data Bus |
- The part of the bus which carries the actual information. - Is bi-directional as data can be sent both ways |
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Address Bus |
- The part of the bus which carries identification about where the data is being sent |
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Control Bus |
- This bus carries command and control signals to and from every other component of a computer |
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PC - Program Counter |
- A register in the control unit which holds the address of the next instruction to be executed |
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MAR - Memory Address Register |
- Holds the address in memory where the processor is required to fetch or store data |
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MDR - Memory Data Register |
- Temporarily holds data moving between the processor and main memory |
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CIR - Current Instruction Register |
- A register in the control unit that stores the address of the next instruction currently being executed and decoded |
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ACC - Accumulator |
- A register within the ALU. - It is used to hold the data currently being processed by the centrol processor. - Any data to be processed is stored temporarily in the accumulator, the results ending up back in the accumulator being stored in the memory unit. |
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ALU - Arithmetic Logic Unit |
- The part of the CPU where data is processed and manipulated. - Consists of arithmetic, logical and shift operations. |
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Register |
- Tiny areas of extremely fast memory located in the CPU normally designed for a specific purpose, where data or control information is stored temporarily. |
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FETCH Stages 1-4 |
1- The address of the next instruction is copied from the PC to the MAR. 2- The instruction held at that address is copied to the MDR. 3- The contents of the PC are incremented. 4- Contents of the MDR are copied to the CIR. |
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DECODE Stages 5-7 |
5- Instruction held in the CIR is decoded. 6- Split into opcode and operand to determine the type of instruction it is. 7- Passed to the accumulator. |
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EXECUTE Stage 8 |
8- Instruction is executed and the result held in accumulator or stored in memory. |
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Opcode |
- Specifies the operation to be carried out. |
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Operand |
1- The address of the data to be used, then copied to the MAR. 2- Actual data to be operated on, which is passed to the MDR. |
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Words |
- Memory is divided up in equal units called words. - Usually in 8, 16, 32 or 64 bits. |
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Clock Speed |
- The faster the clock speed, the more cycles per second, therefore th faster a computer can fetch, decode and execute. - Heats up the faster it goes. |
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Number of Cores |
- Majority of computers have multiple cores. - Each core is theoretically able to process a different instruction at the same time. Computer cant handle the quad-core leading to unused cores. |
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Cache |
- Small amount of superfast memory that stores data and instructions that have recently been used by the processor. - Made out of transistors. - Superfast due to it being close to the CPU. |
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Pipelining |
- Technique used to increase performance, overlapping stages of the cycle. - An instruction enters the pipeline and as soon as one stage has been completed, another instruction enters. |
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Von Neumann Architecture |
- Instructions and data are stored in a common main memory and transferred using a single shared bus. ISSUE - Von Neumann bottleneck - Bus going both ways. Only one instruction at a time. To prevent, add cache. - Simplifies the design of the control unit. |
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Harvard Architecture |
- Seperates data and instructions into seperate memories using different buses. - Used in embedded systems where speed takes priority over design (Washing machine) - 2 buses means its more complicated and expensive. |
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Contempary Architecture |
- Incorparate aspects of both Von Neumann and Harvard architecture. - Cache memory is divided into instruction cache and data cache. - Retrieved using Harvard architecture. |
