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155 Cards in this Set
- Front
- Back
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A * B = ?
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B * A
(Commutative) |
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A + (B+C)= ?
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(A+B)+C
(Associative) |
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A(BC) = ?
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(AB)C
(Associative) |
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A(B+C) = ?
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AB + AC
(Distributive) |
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(A+B)(C+D) = ?
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AC + AD + BC +BD
(Distributive) |
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//A = ?
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A
(Double Inversion) |
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/(AB) = ?
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/A+/B
(DeMorgan) |
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/(A+B) = ?
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/A/B
(DeMorgan) |
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A + AB = ?
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A
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(A+B)(A+C) = ?
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A+BC
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A+/AB = ?
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A+B
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A * 0 = ?
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0
(AND) |
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A * 1 = ?
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A
(AND) |
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A * A = ?
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A
(AND) |
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A * /A = ?
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0
(AND) |
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A + 0 = ?
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A
(OR) |
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A + 1 = ?
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1
(OR) |
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A + A = ?
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A
(OR) |
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A + /A = ?
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1
(OR) |
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A (+) 0 = ?
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A
(XOR) |
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A (+) 1 = ?
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/A
(XOR) |
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A (+) A = ?
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0
(XOR) |
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A (+) /A = ?
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1
(XOR) |
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A decoder is defined as
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a circuit which converts an n-bit input codeword into m lines of output, where m is less than or equal to 2^n
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An encoder is defined as
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a circuit which converts n lines of input into a m-bit codeword, where n is less than or equal to 2^m.
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A demultiplexer is defined as
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gates one input of data line to one out of 2^n output lines.
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A multiplexer is defined as
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gates one of 2^n data inputs to a single output, which is just the opposite operation of a demultiplexer.
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Read-Only Memories (ROM's) are constructed from which of the following components?
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A DECODER and an ENCODER
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If a sequential circuit possesses N memory elements (binary cells or flip flops), what is the maximum number of states could it have?
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2^N
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In general, the PRESENT STATE of a sequential logic circuit is determined by the
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MEMORY ELEMENTS
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What are the 2 D flip-flop operations
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D = 0 is RESET: Qn+1 = 0
D = 1 is SET: Qn+1 = 1 |
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Anything AND'ed with a 0 is equal to....
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0
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Anything AND'ed with a 1 is equal to...
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itself
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Anything OR'ed with a 0 is equal to...
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itself
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Anything OR'ed with a 1 is equal to...
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1
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Anything AND'ed with itself is equal to....
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itself
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Anything OR'ed with itself is equal to....
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itself
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NOT Gate
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Takes a bit as input and produces opposite as output
A Q 0 1 1 0 |
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AND Gate
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If A is 1 AND B is 1, output Q should be 1
A B Q 0 0 0 1 0 0 0 1 0 1 1 1 |
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OR Gate
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If A is 1 OR B is 1 OR Both are 1 then Q is 1
A B Q 0 0 0 1 0 1 0 1 1 1 1 1 |
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NOR Gate
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(NOT and OR, or OR inverted)
A B Q 0 0 1 1 0 0 0 1 0 1 1 0 |
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NAND Gate
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(NOT and AND, or AND inverted)
A B Q 0 0 1 1 0 1 0 1 1 1 1 0 |
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XOR Gate
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Exclusive OR. If either A OR B is 1, but not both, Q is 1
A B Q 0 0 0 1 0 1 0 1 1 1 1 0 |
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XNOR Gate
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If both A and B are the same, Q is 1
(Easiest to think of as an inverted XOR) A B Q 0 0 1 1 0 0 0 1 0 1 1 1 |
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Muxes, Decoders, and full adders are ________ logic circuits
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Combinational Logic Circuts
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Building blocks for finite state machines
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Sequential Logic Circuits
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Have no capacity of storing information
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Combinational Logic Circuits
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What does FSM stand for?
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Finite State Machine
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What does an FSM consist of ?
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1. finite number of states
2. finite number of external inputs 3. finite number of external outputs 4. Specification of all possible state transitions 5. specification of what determines each external output value |
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A State Diagram or Finite-State-Machine (FSM) is?
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- A way to describe desired behavior of sequential circuit
- List states, and transitions among states |
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AA+A!B+BA+B!B
A+A!B+BA+0 (A!B+BA) = A A+A+0 A |
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A+B = A+!A*B
A(A+!AB) AA+A!AB A+(A!A=0)B A+0*B A |
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A(+)B = A*!B+!A*B
A(+)A = A*!A+!A*A 0+0 = 0 |
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Primary memory is ______
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Volatile
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Cache Memory also known as
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Static RAM (SRAM)
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What is the memory element for SRAM?
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Flip flop - 6 to 8 transistors
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What are the advantages of SRAM
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- Stable memory function
- Fast Access |
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What are the disadvantages of SRAM?
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- High power consumption
- High Price - Low Density |
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Main memory is usually known as
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Dynamic RAM (DRAM)
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What is the memory element for DRAM?
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1 transistor and a parasitic Capacitor (Charged capacitor is 1, discharged is 0)
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What are the disadvantages of DRAM?
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- Unstable memory function
- Noise sensitive capacitor - Whole memory discharge - Capacitor needs recharged every 5 milliseconds - Slow Access time because of refresh rate |
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What are the advantages to DRAM
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- High density (1 transistor)
- High Capacity - Low Price - Less power consumption |
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A(+)B
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A*!B+!A+B
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A!B+!AB
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A(+)B
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A(+)A
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A*!A+!AA = 0
so 0!!!! |
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A+0
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A
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A*1
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A
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A+1
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1
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A*0
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0
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A+!A
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1
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A*!A
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0
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A+B
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BA
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A+(B+C)
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(A+B)+C
A+B+C |
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A*(B*C)
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(A*B)*C = A*B*C
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A(B+C)
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A*B+A*C
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AB+AC
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A(B+C)
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A+(B*C)
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(A+B)*(A+C)
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_____
A*B |
__ __
A + B |
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____
A+B |
___ __
A * B |
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A+A
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A
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A*A
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A
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!A*B+A*B
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B
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A+!A*B
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A+B
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A*(A+B)
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A
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