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25 Cards in this Set
- Front
- Back
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Name 2 Factors of CPU Performance. |
1) Instruction Count 2) CPI and Cycle Time |
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Name 2 simple memory reference MIPS codes. |
lw, sw |
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Name 2 MIPS codes for control transfer |
beq, jump |
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A low-voltage and high voltage corresponds to what? |
A 0 and a 1 in binary. |
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How many bits per wire? |
ONE!!!!!!!!!!!!!!!!! |
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State a logic equation for the and, or, mux, and ALU gates and units. Let Y be the output and A and B be inputs. |
And: Y = A & B Or: Y = A | B Mux: Y = S ? A : B ALU: Y = F (A, B) |
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How does a Mux perform 32-bit operations? |
It's arrayed 32 times with a mux for each bit in the word. |
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Name the sequential elements of a CPU that only updates on a clock edge and when the control is set to 1. |
- Register - Memory - Porn |
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How do you calculate the target address of a branch instruction? |
sign-extend the first 16 bits shift the word 4 bits to the left or multiply by 4 |
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An R-Type instruction reserves how many bits for it's op and funct, rs, rt, rd, and shamt? |
6 + 6 + 5 + 5 + 5 + 5 = 32 op + funct + rs + rt + rd + shamt according to math? |
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A Branch instruction reserves how many bits for its op, rs, rt, and address? |
6 + 5 + 5 + 16 = 32 op + rs + rt + address
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A branch instruction is what type of instruction? |
I-Type |
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RegDst does what when Deasserted? When Asserted? |
RegDst 0 - The register destination for RegWrite comes from the rt field. bits 20:16. 1 - register destination for RegWrite comes from bits 15: 11 the rd field. |
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RegWrite does what when Deasserted? When Asserted? |
RegWrite 0 - Nothing is done. 1 - The register from the RegDst is written with the value on the WriteData input. |
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ALUsrcs does what when Deassrted? When asserted? |
ALUsrc 0 - The Second ALU operand comes from the second register file output. 1- The second ALU operand is the sign extended lower 16 bits of the instruction. |
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PCsrc? |
PCsrc 0 - PC is replaced by PC + 4 calculated from an Adder. 1 - PC is replaced by the branch target calculated by an adder. |
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MemRead? |
MemRead 0 - nothing 1 - Data memory contents designated by the address input are put on the read data output. |
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MemWrite? |
MemWrite 0 - nothing 1 - Data memory contents designated by the address input are replaced by the data on the Write Data input. |
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MemtoReg? |
MemtoReg 0 - Value fed to register write data input comes from ALU. 1 - Value fed to register write data input comes from Memory. |
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What is pipelining? |
A form of computer organization in which successive steps of an instruction sequence are executed in turn by a sequence of modules able to operate concurrently, so that another instruction can be begun before the previous one is finished. ex. 3 People doing laundry Non-Pipelined Washer --> Dryer --> Fold --> Next Person Pipelined Washer --> Dryer --> Fold Washer --> Dryer --> Fold Washer --> etc..... |
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What are some thing's that might delay pipelining? |
Structure Hazard - A Required Resource is too busy Data Hazard - A previous instruction needs to complete it's data read and write. Control Hazard - Deciding on control actions depends on previous instruction. |
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How might you prevent a Data Hazard? |
Forwarding the data to the next instruction rather than waiting for the previous instruction to complete. This requires extra connections. This does not always work, for example. If the data you want to forward has not been computed. Code Scheduling or re-ordering the code so that Data Hazard does not occur is also a way to prevent Data Hazard. |
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How does Pipelining improve performance? |
By increasing instruction throughput. Executing instructions in parallel. Each instruction will have the same latency. |
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What is bad about pipelining? |
It's subject to hazards. Instruction set design affects the complexity of pipelining implementation. |
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Who is the B.O.S.S? |
vvvvvvvvvvvvvvvvvvvv --->Julius Gregorio Martin<------ ^^^^^^^^^^^^^^^^^^^ |
