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112 Cards in this Set
- Front
- Back
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Data
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Memory- Primary Storage Bits (0 & 1's)
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Distributed Computing |
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Open computing |
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Standards |
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Protocols HTTP TCP/IP SATA CGI |
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VonNeumann Architecture Why Binary? Bits (0 or 1) Significance of Base 2 |
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System Plumbing System Solar System |
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Decomposition |
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Three-tierarchitecture client server database |
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Data formats representing AlphanumericCharacters ASCII Unicode EBCDIC |
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Bitmap Images Paint &Photo-editing Programs, Pixels, Little CPU Processing Power & |
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Large files - Resolution |
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Object Images Mathematical Formulas, Small files, Lots of CPU processingpower |
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Video Images Streaming Video MPEG-2 Files |
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Audio Formats WAV MP3 MIDI |
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Machine Language |
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Compilers & Interpreters |
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Linkers & Loaders
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Instructions |
directions given to a computer. It causes electrical signals to be sentthrough specific circuits for processing.
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Instruction Sets |
a design that defines functions performed by theprocessor. differentiates computerarchitecture by the number of instructions, the complexity of operationsperformed by individual instructions, the data types supported, the format(layout, fixed vs. variable length), the use of registers and the addressing(size, modes). |
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Instruction Elements |
OPCODE
Source Operand Result or destination Operand |
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ALU |
a major component of the CPUwhere data is held temporarily and the calculations take place. |
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CU |
a major component of the CPUthat performs the fetch/execute cycle. Its function is to control and interpret the execution of instructions. It is also responsible for the retrieval ofinstructions from memory followed by movements of data or addresses from onepart of the CPU to another. |
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Registers |
a single, permanent storagelocation within the CPU used for a particular, defined purpose. It is manipulated directly by the ControlUnit. used to hold a binary valuetemporarily for storage, for manipulation, and/or for simple calculations. is wired within the CPU to perform its specificrole. It can hold data, an address or aninstruction |
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Operation of Memory Memory Mantra |
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RAM (Random Access Memory) DRAM (dynamic RAM) SRAM (static RAM or cache) |
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ROM (Read Only Memory) BIOSand CMOS Chip |
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EEPROM |
allow their program to bechanged by applying a high voltage to the chip to erase it. |
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EPROM |
can also have their programschanged by using a special ultraviolet light to change the program. |
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Two types of booting |
hard(or cold) boot - involves turning on the power initially with theoff/on switch soft(or warm) boot - involves restarting/rebooting the computer |
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Bus |
the physical connection that makes it possibleto transfer data from one location in the computer system to another location. It is a group of electrical or optical conductorsfor carrying computer signals from one location to another location. used most commonly for transferring the databetween the following: the computer peripherals and the CPU; the CPU and memory;and different points within the CPU |
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Parallel Bus |
simply a bus in which there is an individualline for each bit of data, address, and control being used. This means that all bits being transferred onthe bus are being transferred simultaneously
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Serial Bus |
is a bus in which data is transferredsequentially, one bit at a time, using a single data line pair
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Bus Lines Types |
SimplexLine Half-DuplexLine Full-DuplexLine |
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SimplexLine
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A unidirectional line
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Half-DuplexLine
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A bidirectional line may carry data one directionat a time
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Full-DuplexLine |
A bidirectional line that carries data in bothdirections at the same time
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Buses and Expansion Slots |
A point-to-point bus is a bus that carries signals from a single specificsource to a single specific destination. It is intended for connection to a plug-in device that is often called aport. A multipoint bus is a bus that is used to connect several pointstogether. An example is an Ethernetnetwork bus. The interfaces betweendifferent buses are called bus interfacebridges. They connect different bustypes. The PCI bus is an example of apopular modern external bus. |
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SATA (Serial Advanced Technology Attachment) |
replaces an older standard,IDE (Integrated Drive Electronics). Itis used primarily as an interface for magnetic and optical disk storagedevices. |
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SCSI (Small Computer System Interface) |
a parallel bus designed for“universal” I/O interfacing. This busprovides addressing for each device. Itis designed to be “daisy-chained”. Eachdevice on the bus is plugged into the previous device. The final device has a terminator to preventsignal bounce. |
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USB (Universal serial bus) USB (12 Mbps), USB 2.0 (480 Mbps), USB 3.0 (4.8 Gbps) |
designed to make installationand configuration of slow I/O devices easy. As many as 127 devices can be daisy-chainedtogether. It uses only a single set ofresources for all devices on the bus (a single IRQ, I/O Address Range and DMAchannel). The devices are hot swappable. |
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FireWire (IEEE 1394) FireWire 1394a (FireWire 400) & FireWire 1394b(FireWire 800) |
designed to make installationand configuration of fast I/O devices easy. It was developed by Apple and as many as 63devices can be daisy-chained together. It must be supported by the operating system. It uses serial transmission of data. |
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PCI (peripheral component interconnect) |
bus is common on Pentiumcomputers and RISC CPUs. It is a newer64-bit version of a high-speed local parallel bus. It serves as the middle layer between thememory bus and expansion buses and also supports bus mastering. |
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PCI Express – video card |
is a very new serial-basedbus. It is not backward compatible witheither the PCI bus or the PCI-X. Ittransmits data in packets (similar to how Ethernet network, USB and FireWiretransmit data). It can be set up inlanes, so several lanes can be combined to provide tremendous transfer speeds. |
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Chip Set |
set of chips on the system board thatcollectively controls the memory cache, external buses and some peripherals
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Accelerated Hub Architecture |
The Intel i800 Series has an__________, whereby all I/O busesconnect to a hub (Hub Interface), which connects to the system bus. two type: North Bridge South Bridge |
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North Bridge
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is a portion of the i800 chip set hub thatconnects faster I/O buses to the system bus.
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South Bridge
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is a portion of the i800 chipset hub that connects slower I/O buses to the system bus. |
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Word size |
is the largest number of bitsthe CPU can process in one operation. |
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Bus speed |
is the speed or frequency atwhich the data on the system board is moving. |
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Processor speed |
is the speed or frequency atwhich the CPU operates internally. |
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Frontside bus |
is the bus that connects the CPU to memory. It is outside the CPU housing on themotherboard
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Backside bus |
is the bus between the CPU and the L2 cache. It is completely contained inside theCPU housing
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CPU Architecture Types |
VLIW- molecules and 32-bit atoms, code-morphing layer EPIC- Intel CISC- Stack RISC- Circular Buffer |
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VLIW Architecture
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architecturesupports the Transmeta Crusoe and Efficeon families of CPU processors. It has a 128-bit instruction bundle called amolecule. It has four 32-bit atoms (atom= instruction). The parallel processingis performed on four instructions simultaneously. The Efficeon CPU extends the Crusoearchitecture to 256 bits, representing eight 32-bit atoms to be executedsimultaneously. This architecture has 64general-purpose registers to assure adequate register space for rapidregister-to-register processing. It alsohas a code-morphing layer that translates instructions on the fly written forother CPUs into molecules. Instructionsare not written directly for the Crusoe CPU. Itreorders the instructions as necessary to eliminate data dependencies and otherbottlenecks. |
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EPIC Architecture
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supportsthe Intel Itanium IA-64 processor family. The basic instruction set architecture is new, although Intel has builtX86 capability into the CPU to support compatibility with its earlierarchitecture. The Intel X86 instructionset is included. Allinstructions are forty-one bits wide. This architecture organizes instructions into bundles prior toexecution. It has a 128-bit instructionbundle with three 41-bit instructions with 5-bits to identify the type ofinstructions in the bundle. |
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CISC Architecture
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it is necessary tosave all registers to memory and also to copy and retrieve the parameters beingpassed. A stack in memory is commonlyused for this purpose. Characteristicsof the CISC architecture include a comparatively few general-purpose registers;a wide variety of addressing techniques; a large number of specialized, complexinstructions and instruction words of varying sizes.
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RISC Architecture
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the registers are arrangedinto a circular buffer that provides a fast, convenient way to pass parametersbetween procedures. This methodtherefore eliminates the need to copy data when moving from procedure toprocedure. The main features of thisdesign include the following: thirty-two general-purpose registers; a singlemode of memory addressing with two simple variations and a fixed length, fixedformat instruction word (4 bytes). |
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Pipelining |
Modern computers overlapinstructions, so that more than one instruction is being worked on at the sametime. This method is known as_________. The basic idea is that as each instructioncompletes a step, the following instruction moves into the stage being vacated. |
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Scalar Processing |
allows the CPU to process oneinstruction (or step) per clock cycle, on the average. |
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Superscaling Processing |
allows the CPU to processmore than one instruction per clock cycle. It has separate fetch and execute cycles as much as possible. It buffers for fetch and decode phases. It uses parallel execution units. |
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Cache Memory – “Secret” storage area Blocks& Tags |
A strategy to enhance memory performance is toposition a small amount of high-speed memory, SRAM, between the CPU and mainstorage. This “secret” storage area
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Cache Controller Hit& Miss |
tries to anticipate what dataor programming code the CPU will request next, and copies that data or programmingcode to the SRAM chips. |
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Hit
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The situation in which the data or instructionis already present in cache memory
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Miss
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The situation in which the request is notalready present in cache memory
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How caching works |
The entire cache operation is managed by thecache controller. This includes tagsearching and matching, write through or write back, and implementation of thealgorithm that is used for cache block replacement. Cache memory works due to aprinciple known as locality of reference. This principle states that at any given time,most memory references will be confined to one or more small regions ofmemory. |
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Buffer |
a holding tank for data thatis commonly used on most hard drives. |
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Virtual Memory |
hard disk space that is used as memory when asystem starts to run low on RAM. Virtualmemory is stored in a swap file and is used to increase the amount of memoryavailable
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RAM Drive |
configured as a virtual harddrive so that frequently used programs can be accessed faster. It is the opposite of virtual memory. |
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Paging Page Frames PageTables |
a method by which thecomputer is able to conceptually separate the addresses used in a program fromthe addresses that actually identify physical locations in memory. |
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Page
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The program is divided intoblocks called ______. They are all the same size. |
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Frames
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Physical memory is dividedinto blocks called _______. They are all the same size. |
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Page Tables
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For each program in memory there is a page table. Page tables are stored in memory, like anyother program or data. |
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Types of I/O modules |
ProgrammedI/O InterruptDriven I/O DirectMemory Access Controllers |
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ProgrammedI/O |
a full instruction fetch/execute cycle that mustbe performed for each and every I/O data word (32 bits) to be transferred. There are I/O data registers and addressregisters in the CPU. Each I/O devicerequires address information. The primaryuse is keyboards.
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Interrupts |
signals that cause the CPU toalter its normal flow on instruction execution. It frees the CPU from waiting for events and provides control forexternal input. |
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DirectMemory Access |
performed when a program inthe CPU initiates a transfer of data using programmed I/O. The CPU can then be bypassed for theremainder of the transfer. The I/Omodule will notify the CPU with an interrupt when the transfer iscomplete. Once this has occurred, thedata is in memory, ready for the program to use. |
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Quantum |
a time between interruptpulses and represents the time each program will have allocated to it. It is issued to ensure that a programvoluntarily gives up control of the CPU. |
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Privileged Instructions |
Most modern computers have aset of instructions known as ________. These instructions are intended for use by anoperating system program. The HALTinstruction is an example. An attempt by a user’s program to executethis type of instruction would result in an illegal instruction interrupt. |
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Peripherals |
devices that are external to the main processingfunction of the computer itself. Theyare external to the CPU. They do notinclude the CPU, memory and power supply
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Hierarchy of Storage Types |
Registers CacheMemory PrimaryStorage SecondaryStorage |
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Registers
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In the hierarchy of storage,access to CPU ________ is essentiallyinstantaneous, since they are actually a part of the CPU. |
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Cache Memory
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In the hierarchy of storage, _______is the fastest memory outside theCPU. A small amount of fast memory that is used tohold current data and instructions. |
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Primary Storage
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refers to both types of RAM, DRAM and SRAM
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Secondary Storage
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refers to hard drives, thumbdrives, CD-ROMs/DVDs and magnetic tape. Data and programs insecondary storage must be copied to primary storage (memory) for CPU access. |
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Magnetic Disk Hardware |
consists of one or more flat,circular platters made of glass, metal, or plastic, and coated with a magneticsubstance. Actuator Arm, Read/Write Head, Platters |
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Parts of Magnetic Disks |
Track Cylinder Sector |
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Track |
With the actuator arm head ina particular position, it traces out a circle on the disk surface as the diskrotates. This circle is known as a ______. Each one contains one or moreblocks of data. |
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Cylinder |
Since each of the tracks on each surface of theplatters all line up, the set of tracks for all of these surfaces form a
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Sector |
On most disks, the surface ofthe disk platter is divided into equally sized pie shaped segments, known as _______. Each one contains one block ofdata, typically 512 bytes, which represents the smallest unit that can beindependently read or written. |
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Head crash |
occurs when the actuator arm comes in contactwith a platter
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Formatting the disk |
The track positions, blocks, and headers must beestablished before the disk may be used
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Disk Arrays |
a grouping of two or more disk drives. It can be used to reduce overall data accesstime by sharing the data among multiple disks and also to increase systemreliability by providing storage redundancy.
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RAID (Redundant array of inexpensive disks) |
a very useful disk array andcan be implemented in two ways. Thesetwo ways are a mirrored array and a striped array with parity. |
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Mirrored Array (RAID 1) |
a RAID configuration, consists of two or moredisk drives where each disk drive is identical. The disks each contain exactly the same data. Reads are faster since some of the data canbe obtained from each of the hard drives. All data must be written to each of the hard drives.
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Striped Array with Parity (RAID 5) |
in a RAID configuration, requiresa minimum of three disk drives. Some ofthe data is stored on each of the drives along with parity information (errorchecking information). If one of thedrives goes bad, a new drive can be obtained and the data can be reconstructedwith the help of the parity information. |
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Optical Storage Technologies |
CD-ROM (700 MB) DV-DROM (4.7 GB) |
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CD-ROM (700 MB) |
a read-only, removable medium with data storagecapacity of about 700 MB. Data are storedin blocks on the disk. The blocks can bearranged in files, with a directory structure similar to that of magneticdisks. On a CD-ROM, a “0” bit isrepresented as a pit. When the laser strikes a pit, light isscattered. On a CD-ROM, a “1” bit is represented as a land. When the laser strikes land, light reflectedinto the light detector. |
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DVD-ROM (4.7 GB) |
is essentially similar to CD-ROMtechnology. The disks are the same sizeand formatted similarly. However, theuse of a laser with a shorter light wavelength (visible red, instead ofinfrared), allows tighter packing of the disk. Each layer can hold approximately 4.7 GB.
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Displays |
an image made up of thousandsof individual pixels (picture elements) arranged to make a large rectangularscreen. Each pixel is a tiny square on it. |
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Raster Scan |
Interlaceddisplays & Progressive scan displays |
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Vector scan |
An alternative to raster scanis ________, in which pixels aredisplayed in whatever order is necessary to trace out a particular image. It could trace a character by following theoutline of the character. It is used forobject images in CAD/CAM applications. They are sometimes used when printing object graphics-based drawings toa plotter. |
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LCDs (Liquid crystal display ) How it works |
technology has become theprevalent means of displaying images. |
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Active matrix monitor |
there is one transistor per cell in the matrix. It guarantees that each cell will receive astrong charge. It is more expensive anddifficult to manufacture. It has abrighter picture
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Passive matrix monitor |
there is one transistor perrow and column in the matrix. Each cellis lit in succession. The display isdimmer since pixels are lit less frequently. |
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OLED Technology Howit works |
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Printers How they work |
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Inkjet printer |
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Thermal wax transfer printer |
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Dye sublimation printer |
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Laser Printers How they work |
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