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40 Cards in this Set
- Front
- Back
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Define arithmetic logic unit (ALU) |
Responsible for calculations and logic operations. The result of its calculations are stored in the accumulator |
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Define control unit (CU) |
Sends signals to the computer to co-ordinate how the processor works. Controls how data moves around the Cpu and how it moves between CPU and memory |
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Define program counter (PC) |
Keeps track of the memory address of the instruction being executed, then getting incremented to point to the next instruction. Will keep being incremented with the FDE cycle |
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Define the accumulator (ACC) |
Stores the results of calculations made by the ALU |
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Define memory address register (MAR) |
Contains the address of the instruction or data to be fetched |
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Define memory data register |
Stores the data that has been fetched |
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Define current instruction register (CIR) |
Once an instruction had been fetched, it's copied into the CIR for executing |
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Define control bus |
The CPU needs to be able to receive and send information between other parts of the computer. For example, the PSU tells the Cpu to stay up when the PSU is steady enough, through the control bus |
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Define data bus |
Handles both data and instructions (in standard Von Neumann architecture) purpose is to allow data to pass from one area to another |
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Define address address bus |
The CPU must be able to define where the content of the data bits is going to or coming from. To do this, there is a separate bus called the address bus. The CPU places the location of the data/instruction on the address bus |
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Define FDE cycle |
The basic operational process of a computer. It's the process instructions and data go through when used by a computers resources |
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Describe the fetch stage of the FDE cycle |
Data or an instruction is fetched from main memory (RAM) through the control bus and the address bus and then stored in registers in the CPU |
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Describe the decode stage of the FDE cycle |
The CPU will understand how to decode the instruction by referring to it's instruction set. The CPU then decodes the instruction so now it knows what the instruction will have to do and where it needs to go to |
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Describe the execute stage of the FDE cycle |
This is the part of the cycle where dats processing actually takes place and the instruction is carried out |
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How could you increase the efficiency of the FDE cycle? |
Make it so each stage of the cycle is working all of the time, the next instruction will be fetched before the previous one has been executed, and the next instruction will be decoded while the current instruction is being executed - PIPELINING |
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What registers are affected by the FDE cycle and how? |
MAR - stores the address of the instruction to be fetched MAR - Stores the data or instruction once fetched PC - stores the address of the next instruction to be fetched CIR - Where the instruction is decoded and executed |
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What factors affect the performance of the CPU? |
Clock speed Multi core systems Cache memory |
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Define clock speed |
How many instruction cycles the CPU can execute in a second. Modern CPU's are generally in gigahertz |
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Define multicore CPU's |
A CPU with more than one processing unit Increases performance as different cores can work on different problems simultaneously Also, multiple cores can work on one problem to complete it quicker |
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Advantages and disadvantages of multicore CPU's |
+more jobs can be done in a shorter time because they are executed simultaneously +tasks can be shared to reduce the load on individual processors and avoid bottlenecks -difficult to develop programs for multicore systems,ensuring that each task has the correct data to work on -results from different cores needs to be combined at the end of processing, which adds to the time taken to execute a program -not all tasks can be split across multiple cores |
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Define cache memory |
A type of memory that sits between the CPU and RAM in order to speed up the process of data sent between them |
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Why is cache memory needed to speed up the process of executing instructions? |
Data/instructions are loaded into the CPU from main memory by the FDE cycle. As memory runs slower than the processor, the CPU will have to wait for RAM to fetch data, resulting in wasted clock cycles and bottlenecks |
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How does cache memory help prevent bottlenecks and wasted clock cycles? |
Cache sits in between the CPU and RAM. Cache runs much faster than RAM so data and instructions that are regularly used are stored in cache memory, meaning they can be retrieved quicker |
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Advantages and disadvantages of cache memory |
+regularly used data retrieved quicker +reduces bottlenecks +can reduce bandwidth requirements and load on other resources -cache memory has a high cost so many CPU's only have a few mb of cache -process slowed down if a cache miss occurs as data has to be fetched from RAM if not found in cache -larger caches take longer to search |
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Define pipelining |
A method to improve efficiency by having multiple processes working simultaneously. For example in the FDE cycle where one instruction is being fetched whilst the previous instruction is being executed. Pipelining does not improve the time that one instruction can be executed, but means that more instructions can be executed quicker |
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Define Von Neumann architecture |
Describes a computer with a single control unit that sequentially works through instructions. Data and instructions are stored in memory together. Instructions and data are both sent along the data bus, meaning that instructions can't be fetched at the same time that data is being sent, causing the Von Neumann bottleneck |
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Define Harvard architecture |
Data and instructions are stored in separate memory units with separate buses. This means that data can be written/read from data memory whilst the next instruction can be read from the instruction memory, removes the Von Neumann bottleneck |
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How does Von Neumann and Harvard architecture differ? |
-in Von Neumann data and instructions are stored in the same memory unit. Harvard separates data and instructions in separate memory units and buses. This means that Von Neumann architecture has to execute instructions sequentially whereas Harvard architecture can read and write data and instructions simultaneously |
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What are some methods of contemporary CPU architecture |
Parallel processing Multicore systems |
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Define reduced instruction set computer (RISC) |
RISC architectures support only a small number of a very simple instructions, which can be completed in a single clock cycle. This means that individual instructions are executed extremely quickly, but more instructions are needed to complete a single task |
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Define complex instruction set computer |
Support a large number of complicated instructions. This means that instructions can take many clock cycles to complete, as a single CISC instruction may be made up of a number of smaller RISC type instructions |
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Compare RISC and CISC |
-CISC's tend to be slightly slower, however they support a much wider range of addressing modes. As a result, writing CISC programs is easier -RISC processors have less processors so generate less heat and consume less power -RISC shortens execution time by reducing average clock cycles per instruction. CISC shortens execution time by reducing the number of instructions |
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Define graphics processing unit (GPU) |
Used to process complex 3d graphics calculations to improve the performance of graphics intensive processes such as 3D animation and gaming |
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List uses of GPU's |
Modelling systems Breaking passwords Video rendering Machine learning (AI) |
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Define a multicore system |
Used to improve the computing power of processors. Von Neumann architecture uses only a single processor so it was necessary to increase the complexity of the CPU |
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Define parallel systems |
A system with multiple processors, often referred to as dual core, quad core etc. |
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How can parallel systems differ? |
They can work together in one task to get it done quicker. Or, work independently to get different tasks done |
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Define co-processors |
An additional processor used for a specific task. Co-processors and the central CPU can operate on different tasks at the same time, which has the effect of speeding up the overall execution of the program |
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Common examples of co-processors |
Floating point units (FPU) GPU's Digital signal processor (DSP) |
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Advantages and disadvantages of multicore systems |
+ more jobs can be done in a shorter time because they are executed simultaneously +Tasks can be shared to reduce the load on individual processors and reduce bottlenecks - not all tasks can be split across multiple processors - difficult to write programs for multicore systems, ensuring that each task has the correct input data to work on - results from different processors need to be combined at the end of processing, adds to the time needed to execute a program |
