Comp Arch Test 2

Front 1

Program Counter

Back 1

Purpose: Holds the address of (i.e. points at) the next instruction to execute

Operation: Loads the next address on a clock transition or resets to the defaultaddress, based on the value of the reset input.

Front 2

Instruction Memory

Back 2

Purpose: provides the next processor operation

Operation: Usually, the program counter’s value is used as an address to retrieve the next operation from memory. In the simple model below, this happens asynchronously.

Front 3

Data Memory

Back 3

Purpose: provide storage for data not in registers, i.e. permanent storage ofinformation or temporary storage if information that doesn’t fit in the registers.

Operation: The address specifies the location to read or write from. Data is onlywritten when enabled, and if memories can store byte, halfword, or wordinformation, select lines control how much data is written. Writes are synchronizedto a clock edge, but reads often occur asynchronously.

Front 4

Register File

Back 4

Purpose: Provides read access to programming registers. If several registers maybe read at the same time, the register file is multi-ported. On instructions that writeto a register, it also accepts a new register value and updates the correspondingregister on a clock transition.

Front 5

ALU

Back 5

Purpose: Perform arithmetic and logical operations on inputs.

Front 6

Extender

Back 6

Purpose: increase the number of bits. Value may be extended as either a signed or unsigned value.

Front 7

Single Cycle Approach

Back 7

One instruction is executed in one clock cycle. The maximum clock speed is limited be the slowest possible instruction.

However, there is no state information needed, so the designs tend to require fewer resistors, and it is still a decent choice for smaller, embedded processors.

Most simple, executes complete instruction every clock cycle.

Front 8

Multicycle Approach

Back 8

Each instruction is broken down into simpler steps, with complex instructions requiring more steps than simpler ones.

This allows expensive chunks of hardware, such as adders, to be used in multiple clock cycles for difference phases of the same instruction.

Possibly different # of clock cycles per instruction. May be smaller than single cycle.

Front 9

Pipelined Approach

Back 9

Different pieces of hardware execute different steps of instructions, like anassembly line. This requires significantly more hardware/transistors than the othertwo approaches, but it can drastically improve performance. This is the approachused by all high-end processors.

Front 10

32kB

Back 10

2^15

Front 11

32bytes

Back 11

2^5

Front 12

Multiplexer

Back 12

Purpose: In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected.

Front 13

Spatial Locality

Back 13

Likely to need data in address that is close to the accessed item.

Front 14

Temporal Locality

Back 14

Likely to reuse data again soon

Front 15

Sequential Locality

Back 15

Code is likely to be accessed in increasing addresses.

Front 16

Explain the differences in the three reasons for cache misses.

Back 16

Compulsory - First time a "cache line" is accessed.

Conflict - Each cache line limited to certain slots and 2 or more cache lines keep evicting each other.

Capacity - The working set > cache size.

Coherence - Data is inconsistent in another cache.

Front 17

6 Things about interrupt-capable devices

Back 17

Cause

Flag-bit

Enable-bit

Priority

Configuration

Vector Address

Front 18

Cause

Back 18

Event that triggers interrupt. Maybe caused by software such as divide by 0, illegal opcode or hardware message received on port.

Front 19

Flag-bit

Back 19

Device specific event indicating the event happened (raised hand)

Front 20

Enable-bit

Back 20

allows device to take control of CU

Front 21

Priority

Back 21

Determines the order that the device is handled

Front 22

Configuration

Back 22

device options as to what is "interesting" or the cause

Front 23

Vector address

Back 23

holds address of devices interrupt service routine (ISR)

Front 24

Port-Mapped I/O

Back 24

Different opcodes than memory access in/out vs load/store

Front 25

Memory-Mapped I/O

Back 25

All instructions are load/stores

Some addresses assigned to I/O devices.

Front 26

Orders of a processor's memory hierarchy

Back 26

Registers

L1 Cache

L2 Cache

L3 Cache

Main Memory

SSD

Magnetic Disk