Reading...
Play button
Play button
Use LEFT and RIGHT arrow keys to navigate between flashcards;
Use UP and DOWN arrow keys to flip the card;
H to show hint;
A reads text to speech;
24 Cards in this Set
- Front
- Back
|
What four main components make a computer?
|
CPU, Main Memory, I/O Devices and Controllers, System Bus
|
|
|
What is the MAR?
|
Memory Address Register - directs CPU on where memory is ABOUT to be read or written.
|
|
|
How is the processor kept busy?
|
By interleaving fast computation tasks with slow communication.
|
|
|
What are Processor Registers?
|
Very fast memory locations within the CPU
|
|
|
What are the two types of Processor Registers?
|
User-accessible and Status
|
|
|
What two types of User-accessible processor registers exist?
|
Data registers and Address Registers
|
|
|
What is the role of data registers in the CPU?
|
Hold input and output values for and from execution
|
|
|
What are the types of Address Registers in the CPU?
|
MAR, MBR, Index, SP
|
|
|
What is the MBR?
|
Holds address where memory was JUST read or written.
|
|
|
What is the Index register in the CPU?
|
Holds the integer offset for a sequence of memory registers.
|
|
|
What is the SP in the CPU?
|
Stack Pointer - holds the address of memory holding temporary data.
|
|
|
What are the subtypes of the Status register in the CPU?
|
IR, PC, PSW
|
|
|
What is the IR?
|
Instruction Register - holds current executing instruction
|
|
|
What is the PC?
|
Program Counter - holds addresses of next instruction.
|
|
|
What is the PSW?
|
Processor Status Word - whether the processor may be interrupted by I/O
|
|
|
Define the role of memory.
|
To hold instructions and data until they are requested by the processor.
|
|
|
What three points are in trade-off in the consideration of memory?
|
Cost, access time and capacity.
|
|
|
Summarise the Memory Hierarchy.
|
Registers, L1 Cache, L2 Cache, RAM, HDD
|
|
|
What is the smallest addressable quantum of memory?
|
Byte - 8-bit
|
|
|
What is the 'word'?
|
Default data size for the processor, depending on width of buses. Typically 16 or 32-bit.
|
|
|
Describe the requirement by processors of Alignment of data.
|
4-byte quantities must start on byte addresses that are multiples of 4.
|
|
|
What is a disadvantage of unaligned data?
|
Processors which allow this may still have to align the data itself, impacting performance
|
|
|
What do we see when a bit sequence is interpreted in the wrong context?
|
Processor fault / Bus error
|
|
|
When else will these errors occur?
|
When data is unaligned when it should be aligned
|
