Cissp - Security Architecture And Design

Front 1

What is temporary storage, high speed memory, immediately accessible to CPU?

Back 1

Registers (buffers)

Front 2

What are resources live in memory called?

Provide process resources that it requests. Process table keeps list of these.

Back 2

Stack

Front 3

What holds different condition bits such as whether CPU should be working in User Mode (problem state) or privileged mode (kernel or supervisor mode)?

Back 3

Program Status Word (PSW)

Front 4

What are Busses? List 2 kinds of busses.

Back 4

commute instructions to memory
Data buses - moves data
Address buses - used for input/output or identify areas of memory to read from/write to
32 bit and 64 bit refer to width of the bus - more data bits per clock cycle

Front 5

What is the name of the type of RAM in which data must be continually and dynamically refreshed so bits don't disappear?
Cheap and slow

Back 5

Dynamic RAM (DRAM)

Front 6

What is the name of the type of RAM which hold bits in memory cells without capacitors? Requires more transistors than DRAM. Faster but takes more space
Fast and expensive

Back 6

Static RAM (SRAM)

Front 7

Type of RAM that is faster than DRAM because can capture next block of data while first is being sent to CPU

Back 7

Extended data out DRAM (EDO DRAM)

Front 8

Type of RAM that builds upon EDO DRAM. Can send more data at once

Back 8

Burst EDO DRAM (BEDO DRAM)

Front 9

What kind of I/O device works with data on fixed sized blocks each with own unique address? Disc drive is an example

Back 9

Block Device

Front 10

What kind of I/O device works with streams of characters without any fixed sizes. Not addressable. A printer, network interface or mouse are examples.

Back 10

Character devices

Front 11

What kind of I/O device signals interrupt the controller indicating it is done? Device may have to wait.

Back 11

Interrupts

Front 12

What kind of recovery continues to function despite failure?

Back 12

Fault tolerant

Front 13

What kind of recovery is it when program execution is terminated and system protected from compromise when hardware or software failure occurs?

Back 13

Fail safe

Front 14

What kind of recovery allows for non-critical processing to be terminated when failure occurs?

Back 14

Fail soft or resilient

Front 15

What kind of recovery is it when the machine switches to hot backup?

Back 15

Failover

Front 16

What does this describe:
Total combination of protection mechanisms within the computer system. Includes hardware, software and firmware.
Enforce rules of how subjects and objects interact
Originated from the Orange Book

Back 16

Trusted Computer Base (TCB)

Front 17

What are 4 functions of the TCB?

Back 17

1) process activation
2) execution domain switching
(when a process needs to call upon a process in a higher protection ring)
3) memory protection
4) I/O operations

Front 18

What is an abstract machine that mediates all access subjects have to objects?

Back 18

Reference Monitor

Front 19

What is the difference between a security policy and a security model?

Back 19

Security policy defines abstract goals and security model provides the how to

Front 20

What operates in the security environment at the highest level of classification of the information within the computer. In other words, all users on that system must have clearance to access the info on that system.

Back 20

Single State Machine

Front 21

What type of security models are interested in the snapshot of the system at a moment in time. Many activities can alter state (state transitions). If something unsafe happens, system must save itself. Error message, reboot, freeze.

Back 21

State Machine Model

Front 22

What type of security model:
Describes strict layers of subjects and objects and defines clear rules that allow or disallow interactions
Provides upper bound and lower bound of authorized access for subjects
Uses security clearance and labels

Back 22

Multi level lattice models

Front 23

What type of security model has one to one relationships between subjects and objects?

Back 23

Matrix models

Front 24

What type of security model help ensure that high level actions (inputs) do not determine what low level users can see (outputs)?
Actions that take place at a higher security level do not affect or interfere with actions at a lower level

Back 24

Noninterference models

Front 25

What type of security model is not as concerned with subject to object relationship?
How data is allowed or not allowed between objects

Back 25

Information flow models

Front 26

What is a covert channel?

Back 26

A way for an entity to receive info in unauthorized way

Caused by:
Improper oversight in development
Improper implementation of access controls
Existence of shared resource between two entities

Front 27

What are the three rules for Bell LaPadula?

Back 27

1. The simple security rule - subject cannot read to a higher security level - no read up
2. *-property rule - subject cannot write to lower security level - no write down
3. Strong star property rule - can only read and write to equal classification.

Front 28

What are the three rules for the Biba model?

Back 28

1. Simple integrity axiom - subject cannot read data from lower integrity level - no read down
2. *-integrity axiom - subject cannot write data to a higher integrity level - no write up
3. Invocation property - cannot request service (invoke) to subjects of a higher integrity

Front 29

Is Clark Wilson an Integrity Model or Confidentiality Model?

Back 29

Integrity model.

Meets all three goals of integrity
1. Subjects can access objects only through authorized programs (access triple)
2. Separation of duties is enforced
3. Auditing is required

Front 30

Describe the Brewer and Nash Model.

Back 30

AKA Chinese Wall model
Protect against conflicts of interest
Based on information flow model

Front 31

What are the 4 levels of TCSEC?

Back 31

A - Verified Protection
B - Mandatory Protection
C - Discretionary Protection
D - Minimal Protection

Front 32

Which evaluation criteria is used in Europe?

Back 32

ITSEC

Front 33

Which evaluation criteria is the Orange Book?

Back 33

TCSEC

Front 34

What is certification?

Back 34

comprehensive technical evaluation of the security components and their compliance for the purpose of accreditation.

Front 35

What is accreditation

Back 35

formal acceptance of the adequacy of a systems security and functionality

Front 36

What are the three rules of Integrity?

Back 36

1. Subjects can access objects only through authorized programs (access triple)
2. Separation of duties is enforced
3. Auditing is required

Front 37

What are the three Integrity goals?

Back 37

1. Preventing unauthorised users from making any modifications
2. Preventing authorised users from making unauthorised modifications
3. Maintaining internal and external consistency

Front 38

What is the Access Triple?

Back 38

Subject and object are oriented by introducing a third access element - programs - resulting in what is called an access triple, which prevents unauthorized users from modifying data or programs

Front 39

What is Abstraction?

Back 39

Finding commonality between objects and exploiting to make objects simpler to manage.

Front 40

What are control units?

Back 40

manages and synchronizes the system while instructions being executed. Fetches and interprets code

Front 41

What is Pipelining?

Back 41

Combines steps of different instructions.

Front 42

What are Complex-Instruction-Set-Computer (CISC)?

Back 42

Performs many operations per instruction

Front 43

What are Reduced-Instruction-Set-Computer (RISC)?

Back 43

Simpler instructions using fewer cycles

Front 44

What is a Scalar processor?

Back 44

execute one instruction at a time

Front 45

What is a Superscalar processor?

Back 45

enables concurrent execution of multiple instructions

Front 46

What is Electrically Erasable ROM (EEPROM)?

Back 46

Flash memory, can be written. More modern form of EPROM

Front 47

What is Direct (absolute) Addressing?

Back 47

CPU addresses memory by directly specifying the address

Front 48

What is Register Direct Addressing?

Back 48

CPU addresses memory by directly specifying the address the registers within a CPU

Front 49

What is Register indirect addressing?

Back 49

CPU addresses memory by addressing the register for the data's address in main memory

Front 50

What is Indexed addressing?

Back 50

CPU addresses memory by using an index register

Front 51

What is Indirect addressing?

Back 51

CPU addresses memory by addressing the desired location of the program in memory