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38 Cards in this Set
- Front
- Back
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1. Absolute code can be generated for ____. A) compile-time binding B) load-time binding C) execution-time binding D) interrupt binding |
Ans: AFeedback: 8.1.2Difficulty: Easy |
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2. _____ is the method of binding instructions and data to memory performed by most general-purpose operating systems. A) Interrupt binding B) Compile time binding C) Execution time binding D) Load-time binding |
Ans: CFeedback: 8.1.2Difficulty: Medium |
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3. An address generated by a CPU is referred to as a ____. A) physical address B) logical address C) post relocation register address D) Memory-Management Unit (MMU) generated address |
Ans: BFeedback: 8.1.3Difficulty: Easy |
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4. Suppose a program is operating with execution-time binding and the physical address generated is 300. The relocation register is set to 100. What is the corresponding logical address?A) 199 B) 201 C) 200 D) 300 |
Ans: CFeedback: 8.1.3Difficulty: Easy |
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5. The mapping of a logical address to a physical address is done in hardware by the ________. A) memory-management-unit (MMU) B) memory address register C) relocation register D) dynamic loading register |
Ans: AFeedback: 8.1.3Difficulty: Medium |
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6. In a dynamically linked library, ____. A) loading is postponed until execution time B) system language libraries are treated like any other object module C) more disk space is used than in a statically linked library D) a stub is included in the image for each library-routine reference |
Ans: DFeedback: 8.1.5Difficulty: Medium |
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7. The _____ binding scheme facilitates swapping. A) interrupt time B) load time C) assembly time D) execution time |
Ans: DFeedback: 8.2Difficulty: Medium |
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8. The roll out, roll in variant of swapping is used ____. A) when a backing store is not necessary B) for the round-robin scheduling algorithm C) for priority-based scheduling algorithms D) when the load on the system has temporarily been reduced |
Ans: CFeedback: 8.2Difficulty: Medium |
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9. _____ is the dynamic storage-allocation algorithm which results in the smallest leftover hole in memory. A) First fit B) Best fit C) Worst fit D) None of the above |
Ans: BFeedback: 8.3.2Difficulty: Easy |
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10. _____ is the dynamic storage-allocation algorithm which results in the largest leftover hole in memory. A) First fitB) Best fit C) Worst fit D) None of the above |
Ans: CFeedback: 8.3.2Difficulty: Easy |
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11. Which of the following is true of compaction? A) It can be done at assembly, load, or execution time. B) It is used to solve the problem of internal fragmentation. C) It cannot shuffle memory contents. D) It is possible only if relocation is dynamic and done at execution time. |
Ans: DFeedback: 8.3.3Difficulty: Medium |
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12. A(n) ____ page table has one page entry for each real page (or frame) of memory. A) inverted B) clustered C) forward-mapped D) virtual |
Ans: AFeedback: 8.6.3Difficulty: Easy |
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13. Consider a logical address with a page size of 8 KB. How many bits must be used to represent the page offset in the logical address?A) 10 B) 8 C) 13 D) 12 |
Ans: CFeedback: 8.5 |
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14. Consider a logical address with 18 bits used to represent an entry in a conventional page table. How many entries are in the conventional page table? A) 262144 B) 1024 C) 1048576 D) 18 |
Ans: AFeedback: 8.5Difficulty: Easy |
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15. Assume a system has a TLB hit ratio of 90%. It requires 15 nanoseconds to access the TLB, and 85 nanoseconds to access main memory. What is the effective memory access time in nanoseconds for this system? A) 108.5 B) 100 C) 22 D) 176.5 |
Ans: AFeedback: 8.5.2Difficulty: Medium |
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16. Given the logical address 0xAEF9 (in hexadecimal) with a page size of 256 bytes, what is the page number? A) 0xAE B) 0xF9 C) 0xA D) 0x00F9 |
Ans: AFeedback: 8.5Difficulty: Medium |
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17. Given the logical address 0xAEF9 (in hexadecimal) with a page size of 256 bytes, what is the page offset? A) 0xAE B) 0xF9 C) 0xA D) 0xF900 |
Ans: BFeedback: 8.5Difficulty: Medium |
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18. Consider a 32-bit address for a two-level paging system with an 8 KB page size. The outer page table has 1024 entries. How many bits are used to represent the second-level page table?A) 10 B) 8 C) 12 D) 9 |
Ans: DFeedback: 8.6.1Difficulty: Medium |
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19. With segmentation, a logical address consists of _____. A) segment number and offset B) segment name and offset C) segment number and page number D) segment table and segment number |
Ans: AFeedback: 8.4.1Difficulty: Easy |
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20. Which of the following data structures is appropriate for placing into its own segment? A) heap B) kernel code and data C) user code and data D) all of the above |
Ans: DFeedback: 8.4Difficulty: Easy |
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21. Assume the value of the base and limit registers are 1200 and 350 respectively. Which of the following addresses is legal? A) 355 B) 1200 C) 1551 D) all of the above |
Ans: BFeedback: 8.1.1Difficulty: Easy |
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22. A(n) ______ matches the process with each entry in the TLB. A) address-space identifier B) process id C) stack D) page number |
Ans: AFeedback: 8.5.2Difficulty: Medium |
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23. Which of the following statements are true with respect to hashed page tables? A) They only work for sparse address spaces. B) The virtual address is used to hash into the hash table. C) A common approach for handling address spaces larger than 32 bits.D) Hash table collisions do not occur because of the importance of paging. |
Ans: CFeedback: 8.6.2Difficulty: Medium |
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24. Which of the following statements regarding the ARM architecture are false? A) There are essentially four different page ranging from 4-KB to 16-MB in size. B) There are two different levels of TLB. C) One or two level paging may be used. D) The micro TLB must be flushed at each context switch. |
Ans: DFeedback: 8.8Difficulty: Difficult |
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25. Which of the following is not a reason explaining why mobile devices generally do not support swapping? A) Limited space constraints of flash memory. B) Small size of mobile applications do not require use of swap space. C) Limited number of writes of flash memory. D) Poor throughput between main memory and flash memory. |
Ans: BFeedback: 8.2.2Difficulty: Difficul |
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40. A relocation register is used to check for invalid memory addresses generated by a CPU. |
Ans: False |
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41. Reentrant code cannot be shared. |
Ans: FalseFeedback: 8.5.4 Difficulty: Easy |
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42. There is a 1:1 correspondence between the number of entries in the TLB and the number of entries in the page table. |
Ans: FalseFeedback: 8.5.2Difficulty: Easy |
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43. Hierarchical page tables are appropriate for 64-bit architectures. |
Ans: False Feedback: 8.6.1Difficulty: Medium |
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43. The ARM architecture uses both single-level and two-level paging. |
Ans: TrueFeedback: 8.8Difficulty: Medium |
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44. Fragmentation does not occur in a paging system. |
Ans: FalseFeedback: 8.5Difficult: Medium |
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45. Hashed page tables are particularly useful for processes with sparse address spaces. |
Ans: TrueFeedback: 8.6.2Difficulty: Easy |
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46. Inverted page tables require each process to have its own page table. |
Ans: FalseFeedback: 8.6.3Difficulty: Medium |
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47. Without a mechanism such as an address-space identifier, the TLB must be flushed during a context switch. |
Ans: TrueFeedback: 8.5.2Difficulty: Medium |
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48. A 32-bit logical address with 8 KB page size will have 1,000,000 entries in a conventional page table. |
Ans: FalseFeedback: 8.5Difficulty: Medium |
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49. Hashed page tables are commonly used when handling addresses larger than 32 bits. |
Ans: TrueFeedback: 8.6.2Difficulty: Easy |
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50. The x86-64 bit architecture only uses 48 of the 64 possible bits for representing virtual address space. |
Ans: TrueFeedback: 8.7.2Difficulty: Medium |
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51. Mobile operating systems typically support swapping. |
Ans: FalseFeedback: 8.2.2Difficulty: Easy |
