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49 Cards in this Set
- Front
- Back
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What is CISC? |
->Complex instruction set computer -> It requires less coding but more work is needed to be done compared to RISC -> It uses a more internal function format compared to RISC -> The Design philosophy is to carry a given task using fewer lines of code instructions ->The processor hardware is capable to handle complex assembly code instructions Uses few registers Uses many instruction formats |
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What is RISC? |
-> Reduced instructions set Compiler -> It requires fewer built-in instructions format than CISC ->It has a more optimized set of instructions than CISC -> The design philosophy is built on lesser complex instructions by breaking up assembly code instructions into a number of simple code instructions Uses simple instructions Uses many registers Makes use of pipelining |
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What is the difference between RISC and CISC? |
RISC uses fewer instructions formats whereas CISC uses many instructions formats RISC have fewer addressing modes whereas CISC have more addressing modes RISC uses single cycle instructions whereas CISC uses multi cycle instructions RISC has faster execution time for instructions whereas CISC has a longer execution time for instructions RISC ensure the pipelining functions correctly whereas CISc is more difficult to carry out pipelining functions RISC has many registers whereas CISC has few registers |
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What is pipelining? |
To process several instructions simultaneously without waiting for the previous instructions to finish |
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What are the stages of pipelining? |
1) Instruction fetch cycle(IF) 2) Instructions decode cycle (ID) 3) Operand fetch cycle(OF) 4) Instruction execution cycle(IE) 5)Write back process(WB) |
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How does pipelining works? |
1) The process of execution instruction by splitting it into number of packets 2) During a clock cycle, the first stage of instruction 1 are implemented 3) During a clock cycle, the second stage of instruction 1 and the first stage of instruction 2 are implemented 4) During a clock cycle, the third stage of instruction 1 and the second stage of instruction 2 and the first stage of instruction 3 are implemented 5) repeat the process until all the instructions have been processed |
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What is interrupt handling? |
It way to discard all instructions in pipelining except those who are in the write back stage |
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How interrupt handling works? |
1) Interrupt handling routine can be applied to the remaining instructions.Once serviced, the processor can restart with the next stage 2) The contents of the 5 stages will be stored into the register which allows current data to be stored and it allows the processor to restore the previous status of the register once interrupt is serviced |
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What is parallel processing? |
An operation that allows the processor to split up and for each part needed to be reach |
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What is SISD? |
Single Instruction Single Data -> A computer architecture that uses a single processor and uses one data source -> It doesn't allow parallel processing as it only has 1 processor -> Each task is processed in a sequential order |
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What is SIMD? |
Single Instruction Multiple Data -> A computer architecture that uses many processors and different data inputs SIMD many processors execute the same instruction using different data sets -> uses many processors -> Processor executes the same instructions but uses different data inputs known as an array processor |
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What is MIMD? |
Multiple Instruction Multiple Data -> A computer architecture that uses many processors which uses a separate data source MIMD many processors using different instructions using different data sets -> Uses multiple processors -> uses a multi-core system -> It takes the instructions independently and each processor can use the data from a separate data source |
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What is MISD? |
Multiple Instruction Single Data ->A computer architecture that uses many processors but shares the same data source MISD many processors using different instructions use the same data set -> It uses several processors -> The processor uses different instructions but uses the same shared data source |
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What are massively parallel computers? |
The linking together of many computers to form one machine with thousands of processors |
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What is a supercomputer? |
A powerful mainframe computer |
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What is a cluster? |
A number of computers are networked together |
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What are the characteristics of massively parallel computers? |
A number of computers are networked together to form a cluster Each processor carries out a part of communication and processing between computers which is achieved by interconnected data pathway working together simultaneously on the same program working collaboratively on the same program communicating via a messaging interface |
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What are virtual machines? |
An emulation of an existing computer system A computer operating system runs within another computer operating system |
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What is a guest operating system? |
The guest OS runs under the control of the host OS It controls the virtual hardware during emulation OS runs within the host OS The OS runs on a virtual machine |
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What is a host operating system |
It is the OS that controls the physical hardware Os that runs on a virtual machine It is the normal OS for the host |
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What are the advantages of the virtual machine? |
The guest os hosted the virtual machine which can be used without impact anything outside of the virtual machine It can run apps that are not compatible with the host computer by using a guest os that is compatible with the app It can emulate old software on a new system by using a compatible guest os as a virtual machine Virtual machine can be use to test new Operating system or new app as it won't crash the host computer if something goes wrong |
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What are the disadvantages of the virtual machine? |
It doesn't have the same performance when running as a guest os compared to running in the original system It is complex to manage and maintain It is difficult to built an in house virtual machine which is expensive for large firm A virtual machine might not be as efficient performance degrades |
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What is the commutative law |
A + B = B+ A(OR) A.B =B.A (AND) |
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What is associative law |
A +(B+C) = (A+B)+C |
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What is distributive law |
A.(B+C) =(A.B) + (A.C) (A+B).(A+C)=A+B.C A+(B.C) =(A+B).(A+C) |
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What is the idempotent law |
A.A =0 (AND) |
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What is the identity law |
1.A =A(AND) 0 + A = A(OR) |
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What is null law? |
0.A=0(AND) 1+A =1(OR) |
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What is inverse law? |
A.A NOT = 0 (AND) 1+A=1(OR) |
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What is absorption law |
A.(A+B)=A A+A.B=A A+(A.B) = A |
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What are de morgan's laws |
A.B NOT = A NOT + B NOT A OR B NOT = A NOT AND B NOT |
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What is half adder? |
It carries out binary addition on 2 bits giving sum and carry |
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What is a full adder? |
2 half adders combined to allow the sum of several binary bits |
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What is the disadvantage of half adder? |
It is unable to deal with addition of several bits |
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What are flip flops? |
An electronic circuit with 2 stable conditions using sequential circuit |
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What is the function of SR - flip flops? |
They are use to store a single bit |
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What is the details of NOR-based half-adder? |
It responds actively to high inputs(1) When s =1 ,Q=1 0 and 0 make no change The initial outputs form the initial inputs Q and Q NOT can't be the same |
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What are the details of a NAND-based half-adder? |
It responds actively to low inputs(0) When S = 0 ,Q =1 1 and 1 makes no change 0 and 0 is unstable |
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What is a sequential circuit? |
The output that depends on the input value produced from the previous output value |
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What is cross-coupling? |
Interconnection between 2 logic gates which makes up a flip flop |
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What are the problems of SR-Flip Flops? |
Invalid S, R needs to be avoided If the input doesn't arrive at the same time; the flip-flops will become unstable |
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What are the uses of JK flip-flops? |
Several flip-flops can be used to produce shift registers in a computer A simple binary counter can be made by linking up several JK flip-flop circuits |
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What do JK flip-flops do? |
It moves an additional clock input, synchronizes inputs J- set K- Clear |
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What do the NOR and NAND-based JK flip flops has? |
It responsive to high inputs(1) 0 and 0 cause no change 1 and 1 flip bits from the original value J to True Set Q =1 K to True Set Q = 0 |
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What are the rules of karnaugh map rules? |
The group can be a row, a column, and a rectangle The group must contain an even number of 1s The group should be large as possible The group should be able to overlap within the above the rules |
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Describe the process of pipelining during the fetch-execute cycle in RISC processors |
Instructions are divided into 5 stagesInstruction fetch (IF), Instruction decode ( ID) operand fetch (OF), instruction execute (IE), writeback result (WB) Each subtask is completed during one clock cycle No two instructions can execute the same stage at the same clock cycle |
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State the purpose of a flip-flop. |
To store a single bit. |
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What are the roles of flip flops? |
Circuit with two states Used for memory to store single bit of data |
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What are the difference between SR flip flop and JK flip flop |
SR flip-flop has undefined whereas JK flip flop is stable JK flip flop has a clock pulse whereas SR flip flop has no clock pulse |
