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42 Cards in this Set

  • Front
  • Back
On a D-Latch, what does the data input control?
Controls what the next state should be.
On a D-Latch, what does the clock input control?
Controls when the state should change.
A D-latch is transparent when
CLK=1
A D flip flip copies D to Q when?
On the rising edge of the clock, and remembers its state at all other times.
What kind of flip-flops reset themselves as soon as RESET becomes true, independent of CLK?
Asynchronously resettable.
What kind of flip-flops reset themselves only on the rising edge of CLK?
Synchronously resettable.
What is a glitch?
When the clock switches at an incorrect time.
What is a race condition?
When a circuit has certain gates that are slower than others.
What do the outputs of Moore machines depend on?
The current state only.
What do the outputs of Mealy machines depend on?
Inputs as well as the current state.
What is clock skew?
The variation in time of the clock reaching all flip-flops; the variation in clock edges.
What are the two most commonly-used hardware description languages?
Verilog and VHDL.
The outputs of sequential logic depend on what?
Both current and prior input values.
What is a register?
A bank of N flip-flops that share a common CLK input, so that all bits of the register are updated at the same time.
What is setup time?
Time for inputs to stabilize before the rising edge of the clock.
What is hold time?
Time the inputs must remain stable after the rising edge of the clock.
What is the aperture time?
The sum of the setup and hold times.
What is the critical path?
The slowest path from the inputs to the outputs. The sum of the propagation delays over that path.
What is the clock-to-Q delay?
The time required for the clock to propagate to the outputs.
What is a hold time constraint?
The input must not change until some hold time after the rising edge of the clock.
What is a hold time violation?
A violation of a hold time constraint.
True or false: a reliable flip-flop must have a hold time shorter than its contamination delay?
True!
The contamination delay of a circuit must be greater than
The hold time + clock skew - clock-to-q.
What is the clock period?
The time between rising edges of a repetitive clock signal.
To avoid hold time violations, what must be true about the contamination delay?
It must be >= hold time + clock skew - clock-to-q contamination delay.
What is metastability?
When the output takes on a voltage in the forbidden zone. Eventually it will resolve the output to a stable state.
What is the minimum clock period?
Min clock period is greater than or equal to c-to-q propagation delay + propagation delay + setup time.
What is the minimum contamination delay through the logic?
Is >= hold time - contamination from c-to-q,
What is the minimum clock cycle time?
>= t_pcq + t_pd + t_setup
What does a flip-flop do on the rising edge of the clock?
Copies D to Q.
What is the aperture time of a circuit?
The sum of the setup and hold times.
The total time for which the inputs must remain stable is called the
aperture time
What is a setup time constraint?
The input must settle no later than the setup time before the next clock edge.
What is a hold time constraint?
The input must not change until some hold time after the rising edge of the clock.
In a D latch, which is inverted--the clock or D?
D
In a D flip-flop, is the clock inverted on the master or slave D-latch?
On the master.
On an SR latch, does R connect directly to Q or Q-not?
Q
Contamination delay
The minimum time from when an input changes until any output starts to change its value.
Propagation delay
The maximum time from when an input changes until the output reaches its final value.
What does ^ mean in Verilog?
XOR
How do you make an XOR in Verilog?
^
True or false: In a Verilog always statement, <= indicates a blocking assignment and = indicates a nonblocking assignment.
False. In a Verilog always statement, = indicates a blocking assignment and <= indicates a nonblocking assignment.