Computer Organization And Design Chapter 4 Vocabulary

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combinational element

Back 1

An operational element, such as an and GATE OR an ALU

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state element

Back 2

A memory element such as a register or a memory

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asserted

Back 3

The signal is logically high or true

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deasserted

Back 4

The signal is logically low or false

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clocking methodology

Back 5

The approach used to determine when data is valid and stable relative to the clock

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edge-triggered clocking

Back 6

A clocking scheme in which all state changes occur on a clock edge

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control signal

Back 7

A signal used for mux selection or for directing the operation of a functional unit

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data signal

Back 8

contains information that is operated on by a functional unit

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datapath element

Back 9

A unit used to operate on or hold data within a processor.
In the MIPS implementation, datapath elements are; instruction and data memories, the register file, the ALU, and adders.

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program counter

Back 10

the register containing the address of the instruction in the program being executed

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register file

Back 11

A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.

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sign-extend

Back 12

used to increase the size of a data item by replicating the high-order sign bit of the original data item in the high order bits of the larger, destination data item

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branch target address

Back 13

The address specified in a branch, which becomes the new program counter if the branch is taken
(Sum of offset field and address of the instruction following the branch)

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branch taken

Back 14

A branch where the branch conditions is satisfied and the PC becomes the branch target

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branch not taken (untaken branch)

Back 15

A branch where the branch condition is false and the PC becomes the address of the instruction that follows the branch

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delayed branch

Back 16

A type of branch where the instruction immediately following the branch is always executed, regardless of if the branch condition is true or not

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truth table

Back 17

logic table with inputs and outputs

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don't care term

Back 18

An element of a logical function where the output does not depend on the values of all the inputs

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opcode

Back 19

the field that indicates the format and operation of an instruction

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single-cycle implementation (single clockcycle implementation)

Back 20

implementation where an instruction is executed in one clock cycle

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pipelining

Back 21

implementation technique where multiple instructions are overlapped in execution

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Structural Hazard

Back 22

When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute

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Data Hazard (pipeline data hazard)

Back 23

when a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction is not yet available

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forwarding (bypassing)

Back 24

method of resolving data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory.

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load-use data hazard

Back 25

a specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction

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pipeline stall (bubble)

Back 26

A stall initiated in order to resolve a hazard

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control hazard (branch hazard)

Back 27

When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed;
the flow of instruction addresses is not what the pipeline expected

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branch prediction

Back 28

A method of resolving a branch hazard that assumes a given outcome for the branch and proceeds from that assumption rather than waiting to ascertain the actual outcome

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latency

Back 29

the number of stages in a pipeline or the number of stages between two instructions during execution

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nop

Back 30

An instruction that does no operation to change state

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flush

Back 31

To discard instructions in a pipeline, usually due to an unexpected event.

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dynamic branch prediction

Back 32

Prediction of branches at runtime using runtime information

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branch prediction buffer(branch history table)

Back 33

a small memory that is indexed by the lower portion of the address of the branch instruction and that contains one or more bits indicating whether the branch was recently taken or not.

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branch delay slot

Back 34

The slot directly after a delayed branch instruction, which in the MIPS architecture is filled by an instruction that doesn't affect the branch.

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branch target buffer

Back 35

Structure that caches the destination PC or destination instruction for a branch

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correlation predictor

Back 36

A branch predictor that combines local behavior of a particular branch and global information about the behavior of some recent number of executed branches

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tournament branch predictor

Back 37

A branch predictor with multiple predictions for each branch and a selection mechanism that chooses which predictor to enable for a given ranch.

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exception (interrupt)

Back 38

An unscheduled event that disrupts program execution; used to detect overflow

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interrupt

Back 39

An exception that comes from outside of the processor (some processors use interrupt for all exceptions)

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vectored interrupt

Back 40

An interrupt for which the address to which control is transferred is determined by the cause of the exception

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imprecise interrupt (imprecise exception)

Back 41

interrupts or exceptions in pipelined computers that are not associated with the exact instruction that was the cause of the interrupt or exception.

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precise interrupt (precise exception)

Back 42

An interrupt or exception that is always associated with the correct instruction in pipelined computers

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instruction-level parallelism

Back 43

The parallelism among instructinos

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multiple issue

Back 44

A scheme whereby multiple instructions are launched in one clock cycle

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static multiple issue

Back 45

An approach to implementing a multiple issue processor where many decisions are made by the compiler before execution

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dynamic multiple issue

Back 46

An approach to implementing a multiple issue processor where many decisions are made by the compiler before execution

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issue slots

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The positions from which instructions could issue in a given clock cycle; by analogy, these correspond to positions at the starting blocks for a sprint.

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Speculation

Back 48

An approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in execution other instructions

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issue packet

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The set of instructions that issues together in one clock cycle; the packet may be determined statistically by the compiler or dynamically by the processor.

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Very Long Instruction Word (VLIW)

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A style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separated opcode fields

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use latency

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Number of clock cycles between a load instruction and an instruction that can use the result of the load with out stalling the pipeline

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loop unrolling

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A technique to get more performance from loops tat access arrays, in which multiple copies of the loop body are made and instructions from different iterations are scheduled together

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register renaming

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The renaming of registers by the compiler or hardware to remove antidependencies

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Antidependence (name dependence)

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An ordering forced by the reuse of a name, typically a register, rather than by a true dependence that carries a value between two instructions

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superscalar

Back 55

An advanced pipelining technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution

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dynamic pipeline scheduling

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hardware support for reordering the order of instruction execution so as to avoid stalls

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commit unit

Back 57

The unit in a dynamic or out of order execution pipeline that decides when it is safe to release the result of an operating to programmer-visible registers and memory

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reservation station

Back 58

A buffer within a functional unit that holds the operands and the operation

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Reorder buffer

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The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register

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out-of-order execution

Back 60

A situation in pipelined execution when an instruction blocked from executing does not caused the following instructions to wait

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in-order commit

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A commit in which the results of pipelined execution are written to the programmer visible state in the same order that instructions are fetched

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microarchitecture

Back 62

The organization of the processor, including the major functional units, their interconnection and control

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architectural registers

Back 63

The instruction set of visible registers of a processor; for example in MIPS, these are the 32 integer and 16 floating point registers

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instruction latency

Back 64

The inherent execution time for an instruction