Comp Org

Front 1

_________ is responsible for fetching program instructions, decoding each instruction that is fectched, and performing the indicated sequence of operations on the correct data.

Back 1

Central Processing Unit (CPU)

Front 2

The ___________ consists of an arithmetic-logic unit and storage units (registers) that are interconnected by a data bus that is also connected to main memory.

Back 2

Datapath

Front 3

A module responsible for sequencing operations and making sure the correct data are where they need to be at the correct time.

Back 3

Control Unit

Front 4

The _______________ carries out logical and arithmetic operations as directed by the control unit.

Back 4

arithmetic-logic unit (ALU)

Front 5

The control unit uses a(n) ___________register to find the next instruction for execution and a (n) _____________ register to keep track of overflows, carries, borrows and the like.

Back 5

Program counter, Status Register

Front 6

_________ are used widely in computer systems as places to store a wide variety of data, such as addresses, program counters, or data necessary for program execution.

Back 6

Registers

Front 7

Every computer contains an internal _______ that regulates how quickly instructions can be executed. The ________ also synchronizes all of the components in the system.

Back 7

Clock

Front 8

_____________ take a programmer's assembly language program, which is really a symbolic representation of the binary numbers, and convert it into binary instructions, or the machine code equivalent.

Back 8

Assemblers

Front 9

How many bits would you need to address a 2M x 32 bits memory if the memory is byte-addressable?

Back 9

23 bits

Front 10

How many bits would you need to address a 2M x 32 bits memory if the memory is word-addressable?

Back 10

21 bits

Front 11

Suppose that a 2M x 16 main memory is built using 256K x 8 RAM chips and memory is word-addressable.
How many RAM chips are necessary?

Back 11

16

Front 12

Suppose that a 2M x 16 main memory is built using 256Kx 8 RAM chips and memory is word-addressable.
How many RAM chips are there per memory word?

Back 12

2

Front 13

Suppose that a 2M x 16 bits main memory is built using 256K x 8 RAM chips and memory is word-addressable.
How many address bits are needed for each RAM chip?

Back 13

18

Front 14

A digital computer has a memory unit with 24 bits per word. The instruction set consists of 250 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory.
How many bits are needed for the opcode?

Back 14

8

Front 15

__________ are events that alter the normal flow of execution in a computer system. They are used for I/O, error handling, and other miscellaneous events, and the system cannot function properly without them.

Back 15

Interrupts

Front 16

______________ interrupts are those interrupts that must be processed in order to keep the system in a stable condition.

Back 16

Nonmaskable

Front 17

In __________addressing, the address of the operand is explicitly stated in the instruction.

Back 17

direct

Front 18

1 NAND 1 is ?

Back 18

0

Front 19

A' EXOR B' is equivalent to

Back 19

A EXOR B

Front 20

A' NAND B' is equivalent to?

Back 20

A AND B

Front 21

A' NAND B' NAND C' ((A'*B'*C')') is equivalent to?

Back 21

A AND B AND C

Front 22

Use DeMorgan's theorem to convert the maxterm (product of sum) expression to a minterm (sum of products) form

Y = ((A+B'+C')*(A'+B+C'))'

Back 22

Y = A' * B* C + A * B' * C

Front 23

Use DeMorgan's theorems to convert the following POS expression to it's SOP form: (A'*B'*C +A*B*C)' = Y

Back 23

(A+B+C') * (A'+B'+C') = Y

Front 24

What state is a J-K flip flop in when J=1 and K=1?

Back 24

Toggle

Front 25

What state is a J-K flip flop in when J=1 and K=0?

Back 25

Set state (to 1)

Front 26

What state is a J-K flip flop in when J=0 and K=1?

Back 26

Reset State (to 0)

Front 27

What state is a J-K flip flop in when J=0 and K=0?

Back 27

Hold state

Front 28

What would be the output of a JK Flip-Flop at the end if J=1 and K=0 for one clock pulse and then J=1 and K=1 for 2 clock pulses?

Back 28

1

Front 29

What would be the output of a JK Flip-Flop (assume 74LS112) at the end if J=0 and K=1 for one clock pulse and then J=1 and K=1 for the next 3 clock pulses? Assume that PS and CLR are both 1.

Back 29

1

Front 30

The turning points in the historical development of computers are based on the technology incorporated into the devices. t/f

Back 30

TRUE

Front 31

The Principle of Equivalence of Hardware and Software supports the claim that it is not possible to build a special purpose computer to perform only word processing.(True or False)

Back 31

False

Front 32

How many milliseconds (ms) are in 0.5 seconds?

Back 32

500

Front 33

One million bytes can be represented as 2^20 bytes.(True or False)

Back 33

TRUE

Front 34

The Principle of Equivalence of Hardware and Software says that hardware and software are basically equivalent, and implementations done via either method will run at the same speeds. t/f

Back 34

FALSE
They will run at different speeds

Front 35

A Hertz is one million cycles per second.(True or False)

Back 35

FALSE

Front 36

Amdahl's Law states that the performance enhancement possible with a given improvement is limited by the amount that the improved feature is used. t/f

Back 36

TRUE

Front 37

Moore's Law states that the density of silicon chips is cut in half every 18 months.(True or False)

Back 37

FALSE
It doubles every 18 months

Front 38

A CPU typically contains a control unit, an arithmetic logic unit, registers, and a program counter. t/f

Back 38

TRUE

Front 39

The levels of integration in circuits discussed in the book include all but which of the following:
A. SSI
B. MSI
C. LSI
D. VLSI
E. all of these are levels of integration in circuits

Back 39

E: All of the above

Front 40

The Von Neumann architecture includes all of the following except:
A. stored program
B. parallel processing
C. a CPU, memory and I/O system
D. sequential processing of instructions

Back 40

B. parallel processing

Front 41

Name and explain the main components of a von Neumann computer.

Back 41

• A central processing unit The main computing unit, where problems are worked out.
• A main memory system Where instructions for programs are stored.
• An I/O system System to interact with humans.

Front 42

The von Neumann architecture, which is the basis for most digital computers today, suffers from the von Neumann bottleneck. Explain.

Back 42

The von Neumann bottleneck is a technical limitation involving the processor and main memory, the bus connecting these cannot operate at the same speed as either the CPU or the memory, so data transfer between them is limited, thus creating a "bottleneck."

Front 43

If Moore's Law is to hold, Rock's Law must fall.(True or False)

Back 43

TRUE

Front 44

Given n bits, how many distinct combinations of the n bits exist?

Back 44

2^n

Front 45

There are 26 characters in the alphabet we use for writing English. What is the least number of bits needed to give each character a unique bit pattern?

Back 45

2^26 bits

Front 46

There are 26 characters in the alphabet we use for writing English. How many bits would we need to distinguish between upper and lowercase version of all 26 characters?

Back 46

6 bits

Front 47

Algorithm

Back 47

A step by step procedure that guaranteed to terminate, such that step is precisely stated and can be carried out by the computer.

Front 48

ISA

Back 48

Specify the set of instructions the computer can carry out.

Front 49

Microarchitecture

Back 49

Detailed organization of the implementation

Front 50

Instruction

Back 50

The most basic unit of processing.

Front 51

Control Unit

Back 51

Keeps track of both where we are within the process of executing the program and where we are in the process of executing each instruction.

Front 52

Instruction Register

Back 52

Holds the instruction being executed.

Front 53

Program Counter

Back 53

Keeps track of which instruction is to be processed next.

Front 54

How may different positive integers can be expressed in k digits using radix r numbers?

Back 54

r^k

Front 55

A computer has a word length of 8 bits (including sign). If 2's complement is used to represent negative numbers. What range of numbers can be stored in the computer?

Back 55

Between -128 and 127

Front 56

A computer has a word length of 8 bits (including sign). If 1's complement is used to represent negative numbers. What range of numbers can be stored in the computer?(Express your answer in decimal)

Back 56

Between -127 and 127

Front 57

How many bits does an "unsigned int" use compared to a regular "int"?

Back 57

They both use the same number of bits.

Front 58

What is the smallest number in 4 bit 2's complement representation

Back 58

-8

Front 59

In order to avoid multiple representations for the same number, floating-point numbers are maintained in ______________ form.

Back 59

Normalized

Front 60

Which of the following factors is not considered to differentiate the instruction set of any computer?
1. Number of bits per instruction.
2. Number of explicit operands per instruction.
3. Operand location.
4. Types of operations.
5. Position of the Opcode in the instruction

Back 60

5. Position of the Opcode in the instruction

Front 61

Instruction set architectures are measured according to following except:
1. Main memory space occupied by a program.
2. Instruction complexity.
3. Instruction length (in bits).
4. Total number of bits in the program counter.

Back 61

4. Total number of bits in the program counter.

Front 62

In____________ machines, when storing a two-byte integer, the least significant byte is followed by the most significant byte.

Back 62

Little endian

Front 63

In____________ machines, the strings and integers are stored in the same order.

Back 63

big endian

Front 64

Regarding architecture design, how will the CPU store data with its Architecture.:

The operands cannot be accessed randomly

Back 64

A stack architecture

Front 65

Regarding architecture design, how will the CPU will store data with its Architecture.:

Results in longer instructions

Back 65

A general purpose register (GPR) architecture

Front 66

Regarding architecture design, how will the CPU store data with its Architecture.:

One operand is in memory, creating lots of bus traffic

Back 66

An accumulator architecture

Front 67

The following operation given in infix notation is equivalent to what postfix notation?

A x B x C + D x E x F

Back 67

ABxCxDExFx+

Front 68

________________specify where an operand is located:

1. Operand locator
2. Operation mode
3. Addressing modes
4. Location Code

Back 68

3. Addressing modes

Front 69

The actual location of an operand is its _____________ .

1. Effective address.
2. Present Location
3. Operand Box Office
4. Operand Memory

Back 69

1. Effective address.

Front 70

Immediate addressing

Back 70

is where the data is part of the instruction.

Front 71

Indirect addressing

Back 71

gives the address of the address of the data in the instruction.

Front 72

Register addressing

Back 72

is where the data is located in a register.

Front 73

Register indirect addressing

Back 73

uses a register to store the address of the address of the data.

Front 74

Direct addressing

Back 74

is where the address of the data is given in the instruction.

Front 75

Based addressing

Back 75

a base register is used instead of an index register.

Front 76

Indexed addressing

Back 76

uses a register (implicitly or explicitly) as an offset, which is added to the address in the operand to determine the effective address of the data.

Front 77

_________ is used to store permanent, or semi-permanent data that persists even while the system is turned off.
1. Dynamic RAM
2. Static RAM - SRAM
3. Read only Memories

Back 77

3. Read only Memories - ROM

Front 78

_____________ consists of capacitors that slowly leak their charge over time. Thus they must be refreshed every few milliseconds to prevent data loss.
1. Dynamic RAM
2. Static RAM - SRAM
3. Read only Memories

Back 78

1. Dynamic RAM - DRAM

Front 79

__________ consists of circuits similar to the D flip-flop
1. Dynamic RAM
2. Static RAM - SRAM
3. Read only Memories

Back 79

2. Static RAM - SRAM

Front 80

The _______________ tells us that once a byte is accessed, it is likely that a nearby data element will be needed soon.
1. principle of uncertainty
2. principle of recurrence
3. principle of locality

Back 80

3. principle of locality

Front 81

Temporal locality

Back 81

Recently-accessed data elements tend to be accessed again

Front 82

Spatial locality

Back 82

Accesses tend to cluster

Front 83

Sequential locality

Back 83

Instructions tend to be accessed sequentially.

Front 84

The ________ is the time required to process a miss, including the time that it takes to replace a block of memory plus the time it takes to deliver the data to the processor.
1. Miss Rate
2. Miss penalty

Back 84

2. Miss penalty

Front 85

Regarding cache memory concepts,
A hit

Back 85

is when data is found at a given memory level

Front 86

Regarding cache memory concepts,
A miss

Back 86

is when data is not found at a given memory level

Front 87

Regarding cache memory concepts,
The hit rate

Back 87

is the percentage of time data is found at a given memory level.

Front 88

Regarding cache memory concepts,
The miss rate

Back 88

is the percentage of time data is NOT found at a given memory level.
also 1- hit rate

Front 89

The purpose of cache memory is

Back 89

to speed up accesses by storing recently used data closer to the CPU, instead of storing it in main memory.

Front 90

In a ______________ cache consisting of N blocks of cache, block X of main memory maps to cache block Y = X mod N.
1. direct mapped
2. fully associative
3. N-way set associative

Back 90

1. direct mapped

Front 91

If a computer that uses direct mapping cache have 10 blocks of cache, block 15 of main memory would be copied to block _________ of cache memory:

Back 91

Block 5

Front 92

Refers to a memory organization in which the memory is accessed by its content (as opposed to an explicit address):

1. Dynamic Random Access Memory
2. Interleaved Memory
3. Associative Memory
4. Explicit Content Memory

Back 92

3. Associative Memory

Front 93

A replacement policy is invoked when it becomes necessary to evict a block from cache whenever the following cache is used:

1. Direct mapped cache
2. Fully associative
3. N-way set associative

Back 93

2. Fully associative
and
3. N-way set associative

Front 94

The disadvantage of __________ is that memory must be updated with each cache write, which slows down the access time on updates. This slowdown is usually negligible, because the majority of accesses tend to be reads, not writes.

Back 94

Write through

Front 95

________________ occurs when the paging process results in the creation of small, unusable clusters of memory addresses.
1. Page faults
2. Memory overlapping
3. Memory fragmentation
4. Blank pages

Back 95

3. Memory fragmentation

Front 96

The virtual address is divided into two fields: A (n)______ field, and a (n) ______ field. The _______ field determines the page location of the address, and the ________ field indicates the location of the address within the page.

Back 96

Page, offset, page, offset

Front 97

In virtual memory, if the __________ is zero in the page table entry for the logical address, this means that the page is not in memory and must be fetched from disk.
1. Offset
2. Dirty bit
3. Valid bit
4. Page flag

Back 97

3. Valid bit