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26 Cards in this Set
- Front
- Back
Program Counter |
Purpose: Holds the address of (i.e. points at) the next instruction to execute Operation: Loads the next address on a clock transition or resets to the defaultaddress, based on the value of the reset input. |
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Instruction Memory |
Purpose: provides the next processor operation Operation: Usually, the program counter’s value is used as an address to retrieve the next operation from memory. In the simple model below, this happens asynchronously. |
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Data Memory |
Purpose: provide storage for data not in registers, i.e. permanent storage ofinformation or temporary storage if information that doesn’t fit in the registers. Operation: The address specifies the location to read or write from. Data is onlywritten when enabled, and if memories can store byte, halfword, or wordinformation, select lines control how much data is written. Writes are synchronizedto a clock edge, but reads often occur asynchronously. |
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Register File |
Purpose: Provides read access to programming registers. If several registers maybe read at the same time, the register file is multi-ported. On instructions that writeto a register, it also accepts a new register value and updates the correspondingregister on a clock transition. |
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ALU |
Purpose: Perform arithmetic and logical operations on inputs. |
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Extender |
Purpose: increase the number of bits. Value may be extended as either a signed or unsigned value. |
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Single Cycle Approach |
One instruction is executed in one clock cycle. The maximum clock speed is limited be the slowest possible instruction. However, there is no state information needed, so the designs tend to require fewer resistors, and it is still a decent choice for smaller, embedded processors. Most simple, executes complete instruction every clock cycle. |
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Multicycle Approach |
Each instruction is broken down into simpler steps, with complex instructions requiring more steps than simpler ones. This allows expensive chunks of hardware, such as adders, to be used in multiple clock cycles for difference phases of the same instruction. Possibly different # of clock cycles per instruction. May be smaller than single cycle. |
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Pipelined Approach
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Different pieces of hardware execute different steps of instructions, like anassembly line. This requires significantly more hardware/transistors than the othertwo approaches, but it can drastically improve performance. This is the approachused by all high-end processors. |
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32kB |
2^15 |
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32bytes |
2^5 |
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Multiplexer |
Purpose: In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected. |
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Spatial Locality |
Likely to need data in address that is close to the accessed item. |
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Temporal Locality |
Likely to reuse data again soon |
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Sequential Locality |
Code is likely to be accessed in increasing addresses. |
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Explain the differences in the three reasons for cache misses. |
Compulsory - First time a "cache line" is accessed. Conflict - Each cache line limited to certain slots and 2 or more cache lines keep evicting each other. Capacity - The working set > cache size. Coherence - Data is inconsistent in another cache. |
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6 Things about interrupt-capable devices |
Cause Flag-bit Enable-bit Priority Configuration Vector Address |
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Cause |
Event that triggers interrupt. Maybe caused by software such as divide by 0, illegal opcode or hardware message received on port. |
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Flag-bit |
Device specific event indicating the event happened (raised hand) |
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Enable-bit |
allows device to take control of CU |
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Priority |
Determines the order that the device is handled |
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Configuration |
device options as to what is "interesting" or the cause |
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Vector address |
holds address of devices interrupt service routine (ISR) |
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Port-Mapped I/O |
Different opcodes than memory access in/out vs load/store |
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Memory-Mapped I/O |
All instructions are load/stores Some addresses assigned to I/O devices. |
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Orders of a processor's memory hierarchy |
Registers L1 Cache L2 Cache L3 Cache Main Memory SSD Magnetic Disk |