Essay about System

642 Words Mar 11th, 2013 3 Pages
IS2202 Computer Systems Architecture

Lecture review pipeline and memory hierarchy

EECS 252 Graduate Computer Architecture

Computer Systems Architecture
Review of Pipeline and cache memory concepts t
Mats Brorsson, professor matsbror@kth.se, tel. 790 4121

Lec 3 – Performance + Pipeline Review
Electrical Engineering and Computer Sciences El t i l E i i dC t S i University of California, Berkeley http://www.eecs.berkeley.edu/~pattrsn http://www‐inst.eecs.berkeley.edu/~cs252

David Patterson

Review from last lecture
• Tracking and extrapolating technology part of architect’s responsibility • Expect Bandwidth in disks DRAM network and Expect Bandwidth in disks, DRAM, network, and processors to improve by at least as
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MAR, MBR, …) Interconnect to move information among regs and FUs

Control Points
• Datapath: Storage, FU, interconnect sufficient to perform the desired functions
– – Inputs are Control Points Outputs are signals Based on desired function and signals
CS252-s06, Lec 02-intro 7



Controller: State machine to orchestrate operation on the data path


• Map each instruction to sequence of RTLs Map each instruction to sequence of RTLs • Collate sequences into symbolic controller state transition diagram (STD) • Lower symbolic STD to control points • Implement controller
3/28/2008 CS252-s06, Lec 02-intro 8

3/28/2008

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