INTRODUCTION: RESI:
The devices that were huge in the earlier days have been reduced by a huge scale to fulfill the technology scaling demand and to maintain a balance between the device functionality and performance, but also obey Moore’s Law. In order to achieve these requirements, the fabrication process has been altered according to different designs. The reliability issues caused by increased temperatures and factors like soft errors and negative-bias temperature instability (NBTI) are degrading the device performance and affecting the design criteria.
The SRAM cells are implemented using register files (RF). SRAM cells are small and used often and susceptible to the errors affecting the reliability of the microprocessor. A single particle …show more content…
This is called as the recovery phase and may take time.
The RF has a high power density and in order to maintain the performance, it is important to keep a check on the temperature of the chip. As and when the temperature of the RF increases it gives rise to a number of faults. The temperature increased also degrades the life of the transistor. This calls for a cooling process that is expensive. Because of the exponential relationship, as the junction temperature is increased, the leakage power …show more content…
However, the bits used to specify source and destination operands is also reduced, thus reducing the number of physical addressable registers.
The power consumption increases when there is a memory spilling. This affects the performance and can be dealt with by increasing the number of physical registers over the registers mentioned by the instruction encoding. In the instruction set, a single RF appears to consist of similar register windows that is used to lessen the switch overhead during real time interrupts with one window accessible at a given time of execution. However, the competence of a low power design with a memory using smaller width bits is high, while the performance may not be up to the mark.
A number of embedded memory applications are loop dominated i.e. most of the time is spent in loops within the same procedure giving rise to code spilling affecting the save and restore that was eliminated by a number of window registers in the same procedure that in turn reduced the code spilling, memory access and power
The devices that were huge in the earlier days have been reduced by a huge scale to fulfill the technology scaling demand and to maintain a balance between the device functionality and performance, but also obey Moore’s Law. In order to achieve these requirements, the fabrication process has been altered according to different designs. The reliability issues caused by increased temperatures and factors like soft errors and negative-bias temperature instability (NBTI) are degrading the device performance and affecting the design criteria.
The SRAM cells are implemented using register files (RF). SRAM cells are small and used often and susceptible to the errors affecting the reliability of the microprocessor. A single particle …show more content…
This is called as the recovery phase and may take time.
The RF has a high power density and in order to maintain the performance, it is important to keep a check on the temperature of the chip. As and when the temperature of the RF increases it gives rise to a number of faults. The temperature increased also degrades the life of the transistor. This calls for a cooling process that is expensive. Because of the exponential relationship, as the junction temperature is increased, the leakage power …show more content…
However, the bits used to specify source and destination operands is also reduced, thus reducing the number of physical addressable registers.
The power consumption increases when there is a memory spilling. This affects the performance and can be dealt with by increasing the number of physical registers over the registers mentioned by the instruction encoding. In the instruction set, a single RF appears to consist of similar register windows that is used to lessen the switch overhead during real time interrupts with one window accessible at a given time of execution. However, the competence of a low power design with a memory using smaller width bits is high, while the performance may not be up to the mark.
A number of embedded memory applications are loop dominated i.e. most of the time is spent in loops within the same procedure giving rise to code spilling affecting the save and restore that was eliminated by a number of window registers in the same procedure that in turn reduced the code spilling, memory access and power