# Vojin G. Oklobdzija

According to our database

Collaborative distances:

^{1}, Vojin G. Oklobdzija authored at least 72 papers between 1982 and 2015.Collaborative distances:

## Awards

## IEEE Fellow

IEEE Fellow 1996, "For contributions to computer architecture.".

## Timeline

#### Legend:

Book In proceedings Article PhD thesis Other## Links

#### On csauthors.net:

## Bibliography

2015

Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2011

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

IEEE J. Solid State Circuits, 2010

J. Low Power Electron., 2010

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Energy efficient implementation of parallel CMOS multipliers with improved compressors.

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008

Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements.

IEEE J. Solid State Circuits, 2007

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006

Energy optimization of pipelined digital systems using circuit sizing and supply scaling.

IEEE Trans. Very Large Scale Integr. Syst., 2006

IEEE J. Solid State Circuits, 2006

Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations.

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations.

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005

IEEE Trans. Very Large Scale Integr. Syst., 2005

IEEE Trans. Very Large Scale Integr. Syst., 2005

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.

Proceedings of the Integrated Circuit and System Design, 2005

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2003

IBM J. Res. Dev., 2003

Proceedings of the Integrated Circuit and System Design, 2003

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.

Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Comparative analysis of double-edge versus single-edge triggered clocked storage elements.

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation.

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

IEEE Trans. Very Large Scale Integr. Syst., 2000

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing.

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

IEEE Trans. Computers, 1998

A unified approach in the analysis of latches and flip-flops for low-power systems.

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results.

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996

Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters.

J. VLSI Signal Process., 1996

J. VLSI Signal Process., 1996

J. VLSI Signal Process., 1996

A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach.

IEEE Trans. Computers, 1996

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology.

IEEE Trans. Very Large Scale Integr. Syst., 1995

Int. J. High Speed Comput., 1995

Int. J. High Speed Comput., 1995

Proceedings of IPPS '95, 1995

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994

J. VLSI Signal Process., 1994

An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis.

IEEE Trans. Very Large Scale Integr. Syst., 1994

Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination.

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

High-Performance Computer Arithmetic and Implementations: Introduction.

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1992

Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.

IEEE Trans. Computers, 1992

1991

J. VLSI Signal Process., 1991

J. VLSI Signal Process., 1991

Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1988

J. Parallel Distributed Comput., 1988

VLSI architecture of a real-time Wigner distribution processor for acoustic signals.

Proceedings of the IEEE International Conference on Acoustics, 1988

1985

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1984

Test Generation for FET Switching Circuits.

Proceedings of the Proceedings International Test Conference 1984, 1984

1982

IEEE Trans. Computers, 1982