Gate Effect On Nanowire Tunneling Field Effect Transistor (TFET)

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Register to read the introduction… We make the body thickness/diameter of 10 nm respectively for DGTFET and SiNW. 1) Device performance Fig. 5. shows the Id-Vg curve for both DGTFET and SiNW at VDS=1.2V:
SiNW vs DGTFET (10nm)
1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 1.00E-15 DG TFET D=10nm
-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20

denoted the Zener tunneling current in equation (4). The tunneling current is proportional to the electric field along the tunneling direction. Hence, a higher electric field along the tunneling direction will lead to a higher Id. However slightly thinner tunneling barrier width WT gives out DGTFET a slightly better subthreshold swing S, as shown in Fig. 6: B. Dimension dependency of the SiNW TFETs In this part of the simulation, we set up the GAA SiNW devices and explore the dimension effect by changing the diameter of the SiNW while keep other device parameters constant. 1) Device performance Fig. 7. Shows the Id-Vg curve for SiNW TFET when diameter varies while keep other device parameters constant. The device operates at VDS =
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Sub-threshold Swing S increases when we decrease the gate length. The Ioff also increases by four orders when we decrease the gate length from 45nm to 16nm. The on state current Ion does not show liner relation with the gate length.This is because the 45nm SiNW TFET device is already well established, while other devices need further optimization. Theoretically, the shorter the gate length, the stronger the electric field would apply on the channel. More channel inversion will cause effectively BGN to pull down the energy band. Therefore, more electrons would tunneling through and we will have a higher Ion and steeper Subthreshold swing S. For the leakage current we still need to find the reason for the four orders increase when shorter gate length was used. We have to draw the energy band diagram to show the gate control of SiNW device. For an easy observation, we draw the band diagram for gate length of 45nm and 16nm for comparison. As we can see from Fig. 16 since the gate length is big, the energy band under gate region has a better ability to prevent the channel-drain junction band downwards from the influence of drain bias. The leakage current needs to tunnel through a big barrier width under zero gate bias. Therefore, the leakage current is suppressed by big tunneling barrier the channel-drain

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