Essay on Course Syllabus

1197 Words Feb 19th, 2014 5 Pages
ENGR 852

Fall 2013

San Francisco State University School of Engineering ENGR 852: Advanced Digital Design (3 units)

Course Objective: This course is designed to teach students advanced topics in digital design, from high level system description down to ASIC implementation. The course begins with a review of the digital design flow and fundamentals of digital design and then moves towards the system level design of digital systems. The design at the system level is done using Verilog hard-ware description language. The students will experience HDL description of digital systems, synthesis, and optimization to gatelevel. The main objectives of the course is   To prepare the student to be an entry-level industrial standard cell
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Main 1. M.D. Ciletti, “Advanced Digital Design with the Verilog HDL (2nd Edition),” (Prentice Hall), 2010. ISBN 0136019285. 2. D.R. Smith and P.D. Franzon, "Verilog Styles for Synthesis," (Pearson Education [Prentice Hall]), 2000.ISBN. 0201618605. Additional 1. Thomas and Moorby, ``The Verilog Hardware Description Language'', 3rd edition, Kluwer Academic. ISBN 0-7923-9723-1. 2. S. Sutherland, S. Davidman, P. Flake, “System Verilog for Design” (Kluwer), 2004, ISBN 1-4020-7350-8. 3. H. Bhatnagar, “Advanced ASIC Chip Synthesis Using Synopsys Design Compiler, Physical Compiler, and PrimeTime”, ISBN 0-7923-7644-7. Class Schedule ENGR 852: Location: Topics:            Introduction to ASIC design Review of combinational and sequential logic design fundamentals Timing design Design of digital hardware using Verilog HDL Design of complex systems Hierarchy and Partitioning Finite State Machines Test benches and verification Low power design Design for test Introduction to FPGAs Monday 6:10pm-8:55pm TH 210

Tentative Weekly Schedule Week 1 2 3 4 5 6 Date 8/26 9/2 9/9 9/16 9/23 9/30 Topics Course overview; Introduction to ASIC Design No Class (Labor Day) Review of combinational sequential logic design; Timing Design; Design of digital hardware using Verilog HDL I Design of digital hardware using
Page 2 of 4

Due

and Homework 1

ENGR 852

Fall 2013

Verilog HDL II 7 8

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