Abstract—This paper presents novel circuit techniques to implement DDR I/O circuit design that can support multiple low-power standards in a state-of-art 7nm CMOS finfet process. Hybrid pull-up driver with a power gating switch is proposed to support a wide range of data rates and output swing levels. The usage of both thin and thick gate oxide devices in the final output stage effectively achieves minimal power consumption while enabling 6.4Gbps/pin data rate. The proposed input receiver directly converts the incoming signal’s common mode levels to the optimal level of the 1st stage amplifier by a replica feedback loop. Frequency peaking technique is also employed to suppress the inter-symbol interference (ISI) and increase overall bandwidth
…show more content…
The biasing circuits are implemented with the switched capacitors, which are equivalent to resistors. The switching frequency of the switched capacitor circuits is made to be adjustable through the digital control blocks since the gate leakage current in the advanced process has a large uncertainty and tends to change over time. The size of the coupling capacitors is chosen large enough to minimize the amplitude loss caused by the charge sharing between the coupling capacitors and gate capacitance of the following …show more content…
3 shows the block diagram of the entire output driver stages. The signal paths are divided into a NMOS pull-up path, an assist PMOS pull-up path and a NMOS pull-down path. Each path has six identical legs, and the number of the legs to be used are chosen by the users through mode register settings. A separate calibration block performs necessary PVT calibration with one replica leg against 240Ω external reference resistor, and shares the calibration results with other pad output drivers. Both low power consumption and high performance are achieved since all the main critical signal propagation path is implemented with the thin gate oxide transistors in VDD power domain.
III. INPUT RECEIVER CIRCUIT DESIGN
One of the biggest challenges in designing input receiver for ground-terminated DDR IO is an extremely low common mode level of the incoming signal. For example, a typical common mode level of LP4 and LP4X input signals is around 130mV, and this goes down as low as 50mV during the training phase to find out the optimal capturing point. A few solutions have been reported, but among them, direct dc-coupled level translation method [7] provides an unique and efficient
The biasing circuits are implemented with the switched capacitors, which are equivalent to resistors. The switching frequency of the switched capacitor circuits is made to be adjustable through the digital control blocks since the gate leakage current in the advanced process has a large uncertainty and tends to change over time. The size of the coupling capacitors is chosen large enough to minimize the amplitude loss caused by the charge sharing between the coupling capacitors and gate capacitance of the following …show more content…
3 shows the block diagram of the entire output driver stages. The signal paths are divided into a NMOS pull-up path, an assist PMOS pull-up path and a NMOS pull-down path. Each path has six identical legs, and the number of the legs to be used are chosen by the users through mode register settings. A separate calibration block performs necessary PVT calibration with one replica leg against 240Ω external reference resistor, and shares the calibration results with other pad output drivers. Both low power consumption and high performance are achieved since all the main critical signal propagation path is implemented with the thin gate oxide transistors in VDD power domain.
III. INPUT RECEIVER CIRCUIT DESIGN
One of the biggest challenges in designing input receiver for ground-terminated DDR IO is an extremely low common mode level of the incoming signal. For example, a typical common mode level of LP4 and LP4X input signals is around 130mV, and this goes down as low as 50mV during the training phase to find out the optimal capturing point. A few solutions have been reported, but among them, direct dc-coupled level translation method [7] provides an unique and efficient