Nano Tech Final

Front 1

List 5 nano technology challenges.

Back 1

DIBL, HCI, Oxide Break Down, RSCE, Punch-Through, Mobility Degradation, and GIDL.

Front 2

List the features to mitigate nano issues.

Back 2

Halo doping (DIBL), deep doping (punch through), raised source/drain (sub & DIBL), thick overlap oxide (GIDL), lightly doped drain (junction), salicidation (DIBL), strained channel (mobility)

Front 3

Explain DIBL and how to fix it.

Back 3

Increase in Vd increases the depletion region around the drain and reduces the control of the gate. This also decreases Vt.

Fix: Halo doping, raised source drain with salicidation.

Front 4

Explain GIDL and how to fix it.

Back 4

When there is a negative gate voltage and a high drain voltage, there is a high E field at the gate to drain overlap. Depletion forms under overlap in drain. E field generates an electron hole pair which are absorbed by the drain and substrate, respectively.

Fix: Thicker oxide at gate drain overlap to reduce the E field. Or LDD.

Front 5

What is the transistor scaling factor for each new process?

Back 5

0.7x

Front 6

How do you reverse bias a diode?

Back 6

Apply a positive voltage to the N side.

Front 7

Explain punch-through and how to fix it.

Back 7

Punch-through is when the depletion regions around the source and drain merge, allowing current to flow which increases with Vds.

Fix: Deep substrate doping.

Front 8

Explain reverse short channel effect and how to fix it.

Back 8

RSCE is when impurities gather at the edge of the source and drain and the halo doping region connects under the channel, then Vt increases to compensate.

Fix: Retrograde doping.

Front 9

Explain mobility degradation and how to fix it.

Back 9

Mobility degradation is due to the vertical electrical field caused by voltage at the gate. This E field reduces the mobility of the carriers and moves them towards the surface.

Fix: Strain engineering.

Front 10

Explain hot carrier injection and how to fix it.

Back 10

At high Vgs and high Vds there is a large E field. This gives carriers a high velocity and some enter the gate oxide. The carriers in the oxide increase Vt and gate leakage.

Fix: Lightly doped drain to reduce drain E field.

Front 11

What is gate oxide breakdown?

Back 11

When electrons with sufficing energy inject into the gate oxide. Over time these can line up in the oxide and slowly degrade the quality of the oxide.

Front 12

Describe gate leakage.

Back 12

Direct tunneling of electrons through the gate oxide. Increases with reduction in oxide thickness.

Front 13

Describe BTBT.

Back 13

Electron in the valence band of p material tunnel to the conduction band of n material.

Front 14

What are the 5 components of gate leakage?

Back 14

Igdo, Igso, Igb, Igcs, Igcd.

Front 15

Total leakage consists of how many components?

Back 15

Eight total. Including 2 BTBT, 1 Sub, and 5 gate.

Front 16

How does temperature effect the three major leakage components?

Back 16

With increase in temperature sub threshold increases exponentially, junction increases moderately, and gate is insensitive.

Front 17

What is adaptive clocking?

Back 17

Using logic to predict when the critical path will be activated. Then scaling down the clock during critical path operation.

Front 18

What is stacking? What are the benefits?

Back 18

Stacking is a way to implement self-reverse biasing. It allows for a positive voltage at the source rather than ground. The benefits of stacking are a negative Vgs (less sub), less Vds (reduces DIBL), and RBB (reduces BTBT).

Front 19

Describe dual Vt.

Back 19

Low Vt in the critical path for performance, high Vt off the critical path to reduce leakage. It can be implemented with multiple lengths, oxides, or doping of transistors to effect the Vt of them.

Front 20

Describe MTCMOS.

Back 20

Multi-Threshold CMOS is a technique that utilizes sleep transistors. A header PMOS is fed a sleep signal while a footer NMOS is fed the inversion of the sleep signal. The sleep transistors are high Vt and greatly reduce leakage while in sleep mode. During active mode, the circuit is in low Vt operation.

Front 21

Describe BCMOS.

Back 21

Boosted Gate CMOS is using a sleep transistor with high Vt and thick Tox to completely cut off leakage.

Front 22

How does body biasing effect Vt?

Back 22

RBB increases Vt, worsens SCE, increases BTBT. FBB is opposite.

Front 23

Describe VTCMOS.

Back 23

Variable Vt CMOS uses body biasing. In standby mode, RBB for low leakage. In active mode, FBB for speed.