Logic Finals - Terms

Front 1

Consists of logic gates whose outputs at any time are determined directly from the present combination of inputs without regard to previous inputs.

Back 1

Combinational Circuits

Front 2

Adds mathematically 2 bits

Back 2

Half adder

Front 3

Adds mathematically 3 bits

Back 3

Full Adder

Front 4

Subtracts 2 bits

Back 4

Half Subtracter

Front 5

Subtracts 3 bits

Back 5

Full Subtracter

Front 6

Produces the arithmetic sum of 2 binary numbers in parallel

Back 6

Binary Parallel Adder

Front 7

Look Ahead Carry Generator Circuit

Back 7

Front 8

Produces an output carry when both Ai and Bi are one

Back 8

Carry generate (Gi)

Front 9

Associated with the propagation of the carry from Ci to C(i+1)

Back 9

Carry Propagate (Pi)

Front 10

Addition of 2 decimal digits in BCD with carry from a previous state

Back 10

BCD Adder

Front 11

Combinational circuit that compares two numbers, A and B, and determines their relative magnitude.

Back 11

Magnitude Comparator

Front 12

Converts binary information from n input lines to a maximum of 2^n unique output lines

Back 12

Decoder

Front 13

Any Boolean function can be expressed in __

Back 13

Sum of Minterms

Front 14

Use a decoder to generate the __ and an external __ to form the sum

Back 14

Minterms - OR gate

Front 15

Has 2^n input lines and n output lines

Back 15

Encoder

Front 16

Combinational circuit that selects binary information from one of many input lines and directs it to a single ouput line

Back 16

Multiplexer

Front 17

A circuit that receives information in a single line and transmits this information to one of 2^n possible output lines.

Back 17

Demultiplexer

Front 18

Consists of a combinational circuit to which memory elements are connected to form a feedback path

Back 18

Sequential Circuit

Front 19

A device with 2 stable states

Back 19

Flip Flops

Front 20

- A device with 2 stable states

- It can maintain a binary state indefinitely until directed by an input signal to switch states

- It remains in one of these states until triggered into the other.

Back 20

Flip Flops

Front 21

Transistor Latch Diagram

Back 21

Back (Definition)

Front 22

RS Flip flop (NOR Latch)

Back 22

Front 23

2 Types of Clocking/Triggering

Back 23

Level Clocking

Edge Triggering

Front 24

Output for the flip flop responds during the high (or low) level of the clock signal

Back 24

Level Clocking

Front 25

The flip flop produces output only on the rising (or falling) edge of the clock signal

Back 25

Edge Triggering

Front 26

Two external inputs that initiates the condition or state of the flip flop.

Back 26

Preset and Clear

Front 27

This represents the amount of time it takes for the output of a gate or flip flop to change states

Back 27

Propagation Delay Time (tp)

Front 28

It is the minimum length of time the data bit must be present before the clock edge hits

Back 28

Setup Time (tsetup)

Front 29

It is the minimum length of time the data bit must be present after the clock edge has struck.

Back 29

Hold Time (thold)

Front 30

Graphical representation of the truth table

Back 30

Karnaugh Map (K-Map)

Front 31

Graphical representation of the truth table

Back 31

Karnaugh Map (K-Map)

Front 32

A set of exactly 2^m adjacent cells containing ones or zeroes

Back 32

Subcubes

Front 33

Identical except in one variable

Back 33

Adjacent

Front 34

Does not affect the system

Could be 1 or 0

Back 34

Don't Cares

Front 35

Other name for Tabulation Method

Back 35

Quine-McCluskey Method

Front 36

Specific step by step procedure that is guaranteed to produce a simplified standard form expression for a function

Back 36

Tabulation Method

Front 37

Those not checked in the table

Back 37

Prime Implicants

Front 38

Prime implicants that cover minterms with a single check in their column

Back 38

Essential Prime Implicants